d2e015d65f
The DMA channel status field was encoding redundant info wrt the DMA MMR config register, and it was doing an incomplete job of checking all DMA channels (some drivers write directly to the config register). So drop the tristate field in favor of a binary atomic field. This simplifies the code in general, removes the implicit need for sleeping, and forces the suspend code to handle all channels properly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
255 lines
6.7 KiB
C
255 lines
6.7 KiB
C
/*
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* dma.h - Blackfin DMA defines/structures/etc...
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*
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* Copyright 2004-2008 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _BLACKFIN_DMA_H_
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#define _BLACKFIN_DMA_H_
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#include <linux/interrupt.h>
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#include <mach/dma.h>
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#include <asm/atomic.h>
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#include <asm/blackfin.h>
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#include <asm/page.h>
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#define MAX_DMA_ADDRESS PAGE_OFFSET
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/*****************************************************************************
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* Generic DMA Declarations
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*
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****************************************************************************/
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/*-------------------------
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* config reg bits value
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*-------------------------*/
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#define DATA_SIZE_8 0
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#define DATA_SIZE_16 1
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#define DATA_SIZE_32 2
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#define DMA_FLOW_STOP 0
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#define DMA_FLOW_AUTO 1
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#define DMA_FLOW_ARRAY 4
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#define DMA_FLOW_SMALL 6
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#define DMA_FLOW_LARGE 7
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#define DIMENSION_LINEAR 0
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#define DIMENSION_2D 1
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#define DIR_READ 0
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#define DIR_WRITE 1
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#define INTR_DISABLE 0
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#define INTR_ON_BUF 2
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#define INTR_ON_ROW 3
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#define DMA_NOSYNC_KEEP_DMA_BUF 0
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#define DMA_SYNC_RESTART 1
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struct dmasg {
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void *next_desc_addr;
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unsigned long start_addr;
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unsigned short cfg;
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unsigned short x_count;
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short x_modify;
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unsigned short y_count;
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short y_modify;
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} __attribute__((packed));
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struct dma_register {
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void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
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unsigned long start_addr; /* DMA Start address register */
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unsigned short cfg; /* DMA Configuration register */
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unsigned short dummy1; /* DMA Configuration register */
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unsigned long reserved;
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unsigned short x_count; /* DMA x_count register */
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unsigned short dummy2;
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short x_modify; /* DMA x_modify register */
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unsigned short dummy3;
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unsigned short y_count; /* DMA y_count register */
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unsigned short dummy4;
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short y_modify; /* DMA y_modify register */
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unsigned short dummy5;
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void *curr_desc_ptr; /* DMA Current Descriptor Pointer
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register */
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unsigned long curr_addr_ptr; /* DMA Current Address Pointer
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register */
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unsigned short irq_status; /* DMA irq status register */
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unsigned short dummy6;
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unsigned short peripheral_map; /* DMA peripheral map register */
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unsigned short dummy7;
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unsigned short curr_x_count; /* DMA Current x-count register */
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unsigned short dummy8;
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unsigned long reserved2;
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unsigned short curr_y_count; /* DMA Current y-count register */
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unsigned short dummy9;
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unsigned long reserved3;
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};
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struct dma_channel {
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const char *device_id;
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atomic_t chan_status;
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volatile struct dma_register *regs;
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struct dmasg *sg; /* large mode descriptor */
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unsigned int irq;
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void *data;
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#ifdef CONFIG_PM
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unsigned short saved_peripheral_map;
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#endif
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};
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#ifdef CONFIG_PM
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int blackfin_dma_suspend(void);
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void blackfin_dma_resume(void);
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#endif
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/*******************************************************************************
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* DMA API's
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*******************************************************************************/
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extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
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extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS];
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extern int channel2irq(unsigned int channel);
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static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
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{
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dma_ch[channel].regs->start_addr = addr;
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}
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static inline void set_dma_next_desc_addr(unsigned int channel, void *addr)
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{
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dma_ch[channel].regs->next_desc_ptr = addr;
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}
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static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
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{
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dma_ch[channel].regs->curr_desc_ptr = addr;
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}
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static inline void set_dma_x_count(unsigned int channel, unsigned short x_count)
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{
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dma_ch[channel].regs->x_count = x_count;
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}
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static inline void set_dma_y_count(unsigned int channel, unsigned short y_count)
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{
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dma_ch[channel].regs->y_count = y_count;
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}
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static inline void set_dma_x_modify(unsigned int channel, short x_modify)
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{
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dma_ch[channel].regs->x_modify = x_modify;
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}
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static inline void set_dma_y_modify(unsigned int channel, short y_modify)
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{
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dma_ch[channel].regs->y_modify = y_modify;
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}
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static inline void set_dma_config(unsigned int channel, unsigned short config)
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{
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dma_ch[channel].regs->cfg = config;
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}
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static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
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{
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dma_ch[channel].regs->curr_addr_ptr = addr;
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}
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static inline unsigned short
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set_bfin_dma_config(char direction, char flow_mode,
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char intr_mode, char dma_mode, char width, char syncmode)
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{
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return (direction << 1) | (width << 2) | (dma_mode << 4) |
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(intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
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}
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static inline unsigned short get_dma_curr_irqstat(unsigned int channel)
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{
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return dma_ch[channel].regs->irq_status;
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}
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static inline unsigned short get_dma_curr_xcount(unsigned int channel)
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{
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return dma_ch[channel].regs->curr_x_count;
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}
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static inline unsigned short get_dma_curr_ycount(unsigned int channel)
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{
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return dma_ch[channel].regs->curr_y_count;
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}
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static inline void *get_dma_next_desc_ptr(unsigned int channel)
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{
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return dma_ch[channel].regs->next_desc_ptr;
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}
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static inline void *get_dma_curr_desc_ptr(unsigned int channel)
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{
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return dma_ch[channel].regs->curr_desc_ptr;
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}
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static inline unsigned short get_dma_config(unsigned int channel)
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{
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return dma_ch[channel].regs->cfg;
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}
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static inline unsigned long get_dma_curr_addr(unsigned int channel)
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{
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return dma_ch[channel].regs->curr_addr_ptr;
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}
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static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
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{
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/* Make sure the internal data buffers in the core are drained
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* so that the DMA descriptors are completely written when the
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* DMA engine goes to fetch them below.
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*/
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SSYNC();
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dma_ch[channel].regs->next_desc_ptr = sg;
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dma_ch[channel].regs->cfg =
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(dma_ch[channel].regs->cfg & ~(0xf << 8)) |
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((ndsize & 0xf) << 8);
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}
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static inline int dma_channel_active(unsigned int channel)
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{
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return atomic_read(&dma_ch[channel].chan_status);
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}
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static inline void disable_dma(unsigned int channel)
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{
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dma_ch[channel].regs->cfg &= ~DMAEN;
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SSYNC();
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}
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static inline void enable_dma(unsigned int channel)
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{
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dma_ch[channel].regs->curr_x_count = 0;
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dma_ch[channel].regs->curr_y_count = 0;
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dma_ch[channel].regs->cfg |= DMAEN;
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}
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void free_dma(unsigned int channel);
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int request_dma(unsigned int channel, const char *device_id);
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int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
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static inline void dma_disable_irq(unsigned int channel)
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{
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disable_irq(dma_ch[channel].irq);
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}
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static inline void dma_enable_irq(unsigned int channel)
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{
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enable_irq(dma_ch[channel].irq);
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}
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static inline void clear_dma_irqstat(unsigned int channel)
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{
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dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR;
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}
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void *dma_memcpy(void *dest, const void *src, size_t count);
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void *safe_dma_memcpy(void *dest, const void *src, size_t count);
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void blackfin_dma_early_init(void);
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void early_dma_memcpy(void *dest, const void *src, size_t count);
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void early_dma_memcpy_done(void);
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#endif
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