74bf4312ff
We now use the TSB hardware assist features of the UltraSPARC MMUs. SMP is currently knowingly broken, we need to find another place to store the per-cpu base pointers. We hid them away in the TSB base register, and that obviously will not work any more :-) Another known broken case is non-8KB base page size. Also noticed that flush_tlb_all() is not referenced anywhere, only the internal __flush_tlb_all() (local cpu only) is used by the sparc64 port, so we can get rid of flush_tlb_all(). The kernel gets it's own 8KB TSB (swapper_tsb) and each address space gets it's own private 8K TSB. Later we can add code to dynamically increase the size of per-process TSB as the RSS grows. An 8KB TSB is good enough for up to about a 4MB RSS, after which the TSB starts to incur many capacity and conflict misses. We even accumulate OBP translations into the kernel TSB. Another area for refinement is large page size support. We could use a secondary address space TSB to handle those. Signed-off-by: David S. Miller <davem@davemloft.net>
40 lines
845 B
ArmAsm
40 lines
845 B
ArmAsm
/* ITLB ** ICACHE line 1: Context 0 check and TSB load */
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ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
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ldxa [%g0] ASI_IMMU, %g6 ! Get TAG TARGET
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srlx %g6, 48, %g5 ! Get context
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brz,pn %g5, kvmap_itlb ! Context 0 processing
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nop ! Delay slot (fill me)
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ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB entry
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cmp %g4, %g6 ! Compare TAG
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sethi %hi(_PAGE_EXEC), %g4 ! Setup exec check
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/* ITLB ** ICACHE line 2: TSB compare and TLB load */
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bne,pn %xcc, tsb_miss_itlb ! Miss
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mov FAULT_CODE_ITLB, %g3
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andcc %g5, %g4, %g0 ! Executable?
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be,pn %xcc, tsb_do_fault
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nop ! Delay slot, fill me
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stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB
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retry ! Trap done
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nop
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/* ITLB ** ICACHE line 3: */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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/* ITLB ** ICACHE line 4: */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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