8f4e956b31
When a machine check or NMI occurs while multiple byte code is patched the CPU could theoretically see an inconsistent instruction and crash. Prevent this by temporarily disabling MCEs and returning early in the NMI handler. Based on discussion with Mathieu Desnoyers. Cc: Mathieu Desnoyers <compudj@krystal.dyndns.org> Cc: Jeremy Fitzhardinge <jeremy@goop.org> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
116 lines
3.2 KiB
C
116 lines
3.2 KiB
C
#ifndef _ASM_MCE_H
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#define _ASM_MCE_H 1
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#include <asm/ioctls.h>
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#include <asm/types.h>
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/*
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* Machine Check support for x86
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*/
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#define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */
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#define MCG_STATUS_RIPV (1UL<<0) /* restart ip valid */
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#define MCG_STATUS_EIPV (1UL<<1) /* eip points to correct instruction */
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#define MCG_STATUS_MCIP (1UL<<2) /* machine check in progress */
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#define MCI_STATUS_VAL (1UL<<63) /* valid error */
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#define MCI_STATUS_OVER (1UL<<62) /* previous errors lost */
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#define MCI_STATUS_UC (1UL<<61) /* uncorrected error */
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#define MCI_STATUS_EN (1UL<<60) /* error enabled */
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#define MCI_STATUS_MISCV (1UL<<59) /* misc error reg. valid */
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#define MCI_STATUS_ADDRV (1UL<<58) /* addr reg. valid */
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#define MCI_STATUS_PCC (1UL<<57) /* processor context corrupt */
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/* Fields are zero when not available */
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struct mce {
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__u64 status;
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__u64 misc;
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__u64 addr;
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__u64 mcgstatus;
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__u64 rip;
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__u64 tsc; /* cpu time stamp counter */
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__u64 res1; /* for future extension */
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__u64 res2; /* dito. */
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__u8 cs; /* code segment */
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__u8 bank; /* machine check bank */
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__u8 cpu; /* cpu that raised the error */
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__u8 finished; /* entry is valid */
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__u32 pad;
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};
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/*
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* This structure contains all data related to the MCE log.
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* Also carries a signature to make it easier to find from external debugging tools.
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* Each entry is only valid when its finished flag is set.
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*/
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#define MCE_LOG_LEN 32
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struct mce_log {
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char signature[12]; /* "MACHINECHECK" */
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unsigned len; /* = MCE_LOG_LEN */
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unsigned next;
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unsigned flags;
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unsigned pad0;
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struct mce entry[MCE_LOG_LEN];
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};
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#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
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#define MCE_LOG_SIGNATURE "MACHINECHECK"
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#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
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#define MCE_GET_LOG_LEN _IOR('M', 2, int)
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#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
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/* Software defined banks */
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#define MCE_EXTENDED_BANK 128
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#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
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#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
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#define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9)
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#define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9)
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#define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9)
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#define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9)
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#define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9)
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#define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9)
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#define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0)
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#ifdef __KERNEL__
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#include <asm/atomic.h>
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void mce_log(struct mce *m);
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DECLARE_PER_CPU(struct sys_device, device_mce);
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#ifdef CONFIG_X86_MCE_INTEL
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void mce_intel_feature_init(struct cpuinfo_x86 *c);
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#else
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static inline void mce_intel_feature_init(struct cpuinfo_x86 *c)
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{
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}
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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void mce_amd_feature_init(struct cpuinfo_x86 *c);
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#else
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)
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{
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}
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#endif
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void mce_log_therm_throt_event(unsigned int cpu, __u64 status);
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extern atomic_t mce_entry;
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extern void do_machine_check(struct pt_regs *, long);
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extern int mce_notify_user(void);
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extern void stop_mce(void);
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extern void restart_mce(void);
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#endif
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#endif
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