51533b615e
New CRIS sub architecture named v32. From: Dave Jones <davej@redhat.com> Fix swapped kmalloc args Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
223 lines
6.3 KiB
C
223 lines
6.3 KiB
C
#ifndef __ata_defs_h
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#define __ata_defs_h
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/*
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* This file is autogenerated from
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* file: ../../inst/ata/rtl/ata_regs.r
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* id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
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* last modfied: Mon Apr 11 16:06:25 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r
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* id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope ata */
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/* Register rw_ctrl0, scope ata, type rw */
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typedef struct {
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unsigned int pio_hold : 6;
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unsigned int pio_strb : 6;
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unsigned int pio_setup : 6;
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unsigned int dma_hold : 6;
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unsigned int dma_strb : 6;
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unsigned int rst : 1;
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unsigned int en : 1;
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} reg_ata_rw_ctrl0;
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#define REG_RD_ADDR_ata_rw_ctrl0 12
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#define REG_WR_ADDR_ata_rw_ctrl0 12
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/* Register rw_ctrl1, scope ata, type rw */
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typedef struct {
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unsigned int udma_tcyc : 4;
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unsigned int udma_tdvs : 4;
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unsigned int dummy1 : 24;
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} reg_ata_rw_ctrl1;
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#define REG_RD_ADDR_ata_rw_ctrl1 16
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#define REG_WR_ADDR_ata_rw_ctrl1 16
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/* Register rw_ctrl2, scope ata, type rw */
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typedef struct {
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unsigned int data : 16;
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unsigned int dummy1 : 3;
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unsigned int dma_size : 1;
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unsigned int multi : 1;
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unsigned int hsh : 2;
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unsigned int trf_mode : 1;
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unsigned int rw : 1;
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unsigned int addr : 3;
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unsigned int cs0 : 1;
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unsigned int cs1 : 1;
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unsigned int sel : 2;
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} reg_ata_rw_ctrl2;
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#define REG_RD_ADDR_ata_rw_ctrl2 0
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#define REG_WR_ADDR_ata_rw_ctrl2 0
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/* Register rs_stat_data, scope ata, type rs */
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typedef struct {
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unsigned int data : 16;
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unsigned int dav : 1;
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unsigned int busy : 1;
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unsigned int dummy1 : 14;
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} reg_ata_rs_stat_data;
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#define REG_RD_ADDR_ata_rs_stat_data 4
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/* Register r_stat_data, scope ata, type r */
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typedef struct {
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unsigned int data : 16;
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unsigned int dav : 1;
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unsigned int busy : 1;
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unsigned int dummy1 : 14;
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} reg_ata_r_stat_data;
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#define REG_RD_ADDR_ata_r_stat_data 8
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/* Register rw_trf_cnt, scope ata, type rw */
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typedef struct {
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unsigned int cnt : 17;
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unsigned int dummy1 : 15;
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} reg_ata_rw_trf_cnt;
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#define REG_RD_ADDR_ata_rw_trf_cnt 20
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#define REG_WR_ADDR_ata_rw_trf_cnt 20
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/* Register r_stat_misc, scope ata, type r */
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typedef struct {
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unsigned int crc : 16;
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unsigned int dummy1 : 16;
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} reg_ata_r_stat_misc;
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#define REG_RD_ADDR_ata_r_stat_misc 24
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/* Register rw_intr_mask, scope ata, type rw */
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typedef struct {
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unsigned int bus0 : 1;
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unsigned int bus1 : 1;
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unsigned int bus2 : 1;
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unsigned int bus3 : 1;
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unsigned int dummy1 : 28;
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} reg_ata_rw_intr_mask;
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#define REG_RD_ADDR_ata_rw_intr_mask 28
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#define REG_WR_ADDR_ata_rw_intr_mask 28
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/* Register rw_ack_intr, scope ata, type rw */
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typedef struct {
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unsigned int bus0 : 1;
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unsigned int bus1 : 1;
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unsigned int bus2 : 1;
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unsigned int bus3 : 1;
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unsigned int dummy1 : 28;
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} reg_ata_rw_ack_intr;
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#define REG_RD_ADDR_ata_rw_ack_intr 32
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#define REG_WR_ADDR_ata_rw_ack_intr 32
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/* Register r_intr, scope ata, type r */
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typedef struct {
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unsigned int bus0 : 1;
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unsigned int bus1 : 1;
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unsigned int bus2 : 1;
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unsigned int bus3 : 1;
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unsigned int dummy1 : 28;
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} reg_ata_r_intr;
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#define REG_RD_ADDR_ata_r_intr 36
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/* Register r_masked_intr, scope ata, type r */
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typedef struct {
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unsigned int bus0 : 1;
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unsigned int bus1 : 1;
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unsigned int bus2 : 1;
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unsigned int bus3 : 1;
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unsigned int dummy1 : 28;
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} reg_ata_r_masked_intr;
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#define REG_RD_ADDR_ata_r_masked_intr 40
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/* Constants */
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enum {
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regk_ata_active = 0x00000001,
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regk_ata_byte = 0x00000001,
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regk_ata_data = 0x00000001,
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regk_ata_dma = 0x00000001,
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regk_ata_inactive = 0x00000000,
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regk_ata_no = 0x00000000,
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regk_ata_nodata = 0x00000000,
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regk_ata_pio = 0x00000000,
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regk_ata_rd = 0x00000001,
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regk_ata_reg = 0x00000000,
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regk_ata_rw_ctrl0_default = 0x00000000,
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regk_ata_rw_ctrl2_default = 0x00000000,
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regk_ata_rw_intr_mask_default = 0x00000000,
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regk_ata_udma = 0x00000002,
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regk_ata_word = 0x00000000,
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regk_ata_wr = 0x00000000,
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regk_ata_yes = 0x00000001
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};
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#endif /* __ata_defs_h */
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