1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
585 lines
14 KiB
C
585 lines
14 KiB
C
/*
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* arch/ppc/platforms/pmac_nvram.c
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*
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* Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Todo: - add support for the OF persistent properties
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/string.h>
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#include <linux/nvram.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/adb.h>
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#include <linux/pmu.h>
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#include <linux/bootmem.h>
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#include <linux/completion.h>
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#include <linux/spinlock.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/nvram.h>
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#define DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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#define NVRAM_SIZE 0x2000 /* 8kB of non-volatile RAM */
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#define CORE99_SIGNATURE 0x5a
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#define CORE99_ADLER_START 0x14
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/* On Core99, nvram is either a sharp, a micron or an AMD flash */
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#define SM_FLASH_STATUS_DONE 0x80
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#define SM_FLASH_STATUS_ERR 0x38
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#define SM_FLASH_CMD_ERASE_CONFIRM 0xd0
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#define SM_FLASH_CMD_ERASE_SETUP 0x20
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#define SM_FLASH_CMD_RESET 0xff
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#define SM_FLASH_CMD_WRITE_SETUP 0x40
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#define SM_FLASH_CMD_CLEAR_STATUS 0x50
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#define SM_FLASH_CMD_READ_STATUS 0x70
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/* CHRP NVRAM header */
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struct chrp_header {
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u8 signature;
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u8 cksum;
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u16 len;
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char name[12];
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u8 data[0];
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};
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struct core99_header {
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struct chrp_header hdr;
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u32 adler;
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u32 generation;
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u32 reserved[2];
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};
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/*
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* Read and write the non-volatile RAM on PowerMacs and CHRP machines.
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*/
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static int nvram_naddrs;
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static volatile unsigned char *nvram_addr;
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static volatile unsigned char *nvram_data;
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static int nvram_mult, is_core_99;
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static int core99_bank = 0;
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static int nvram_partitions[3];
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static DEFINE_SPINLOCK(nv_lock);
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extern int pmac_newworld;
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extern int system_running;
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static int (*core99_write_bank)(int bank, u8* datas);
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static int (*core99_erase_bank)(int bank);
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static char *nvram_image __pmacdata;
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static unsigned char __pmac core99_nvram_read_byte(int addr)
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{
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if (nvram_image == NULL)
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return 0xff;
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return nvram_image[addr];
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}
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static void __pmac core99_nvram_write_byte(int addr, unsigned char val)
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{
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if (nvram_image == NULL)
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return;
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nvram_image[addr] = val;
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}
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static unsigned char __openfirmware direct_nvram_read_byte(int addr)
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{
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return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
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}
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static void __openfirmware direct_nvram_write_byte(int addr, unsigned char val)
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{
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out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
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}
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static unsigned char __pmac indirect_nvram_read_byte(int addr)
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{
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unsigned char val;
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unsigned long flags;
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spin_lock_irqsave(&nv_lock, flags);
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out_8(nvram_addr, addr >> 5);
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val = in_8(&nvram_data[(addr & 0x1f) << 4]);
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spin_unlock_irqrestore(&nv_lock, flags);
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return val;
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}
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static void __pmac indirect_nvram_write_byte(int addr, unsigned char val)
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{
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unsigned long flags;
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spin_lock_irqsave(&nv_lock, flags);
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out_8(nvram_addr, addr >> 5);
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out_8(&nvram_data[(addr & 0x1f) << 4], val);
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spin_unlock_irqrestore(&nv_lock, flags);
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}
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#ifdef CONFIG_ADB_PMU
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static void __pmac pmu_nvram_complete(struct adb_request *req)
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{
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if (req->arg)
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complete((struct completion *)req->arg);
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}
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static unsigned char __pmac pmu_nvram_read_byte(int addr)
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{
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struct adb_request req;
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DECLARE_COMPLETION(req_complete);
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req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
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if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
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(addr >> 8) & 0xff, addr & 0xff))
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return 0xff;
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if (system_state == SYSTEM_RUNNING)
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wait_for_completion(&req_complete);
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while (!req.complete)
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pmu_poll();
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return req.reply[0];
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}
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static void __pmac pmu_nvram_write_byte(int addr, unsigned char val)
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{
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struct adb_request req;
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DECLARE_COMPLETION(req_complete);
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req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
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if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
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(addr >> 8) & 0xff, addr & 0xff, val))
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return;
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if (system_state == SYSTEM_RUNNING)
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wait_for_completion(&req_complete);
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while (!req.complete)
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pmu_poll();
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}
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#endif /* CONFIG_ADB_PMU */
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static u8 __pmac chrp_checksum(struct chrp_header* hdr)
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{
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u8 *ptr;
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u16 sum = hdr->signature;
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for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
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sum += *ptr;
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while (sum > 0xFF)
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sum = (sum & 0xFF) + (sum>>8);
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return sum;
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}
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static u32 __pmac core99_calc_adler(u8 *buffer)
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{
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int cnt;
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u32 low, high;
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buffer += CORE99_ADLER_START;
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low = 1;
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high = 0;
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for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
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if ((cnt % 5000) == 0) {
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high %= 65521UL;
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high %= 65521UL;
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}
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low += buffer[cnt];
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high += low;
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}
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low %= 65521UL;
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high %= 65521UL;
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return (high << 16) | low;
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}
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static u32 __pmac core99_check(u8* datas)
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{
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struct core99_header* hdr99 = (struct core99_header*)datas;
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if (hdr99->hdr.signature != CORE99_SIGNATURE) {
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DBG("Invalid signature\n");
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return 0;
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}
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if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
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DBG("Invalid checksum\n");
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return 0;
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}
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if (hdr99->adler != core99_calc_adler(datas)) {
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DBG("Invalid adler\n");
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return 0;
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}
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return hdr99->generation;
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}
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static int __pmac sm_erase_bank(int bank)
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{
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int stat, i;
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unsigned long timeout;
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u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
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out_8(base, SM_FLASH_CMD_ERASE_SETUP);
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out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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printk(KERN_ERR "nvram: Sharp/Miron flash erase timeout !\n");
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break;
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}
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out_8(base, SM_FLASH_CMD_READ_STATUS);
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stat = in_8(base);
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} while (!(stat & SM_FLASH_STATUS_DONE));
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out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
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out_8(base, SM_FLASH_CMD_RESET);
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for (i=0; i<NVRAM_SIZE; i++)
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if (base[i] != 0xff) {
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printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
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return -ENXIO;
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}
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return 0;
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}
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static int __pmac sm_write_bank(int bank, u8* datas)
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{
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int i, stat = 0;
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unsigned long timeout;
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u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
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for (i=0; i<NVRAM_SIZE; i++) {
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out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
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udelay(1);
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out_8(base+i, datas[i]);
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
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break;
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}
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out_8(base, SM_FLASH_CMD_READ_STATUS);
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stat = in_8(base);
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} while (!(stat & SM_FLASH_STATUS_DONE));
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if (!(stat & SM_FLASH_STATUS_DONE))
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break;
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}
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out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
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out_8(base, SM_FLASH_CMD_RESET);
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for (i=0; i<NVRAM_SIZE; i++)
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if (base[i] != datas[i]) {
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printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
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return -ENXIO;
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}
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return 0;
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}
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static int __pmac amd_erase_bank(int bank)
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{
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int i, stat = 0;
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unsigned long timeout;
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u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: AMD Erasing bank %d...\n", bank);
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/* Unlock 1 */
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out_8(base+0x555, 0xaa);
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udelay(1);
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/* Unlock 2 */
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out_8(base+0x2aa, 0x55);
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udelay(1);
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/* Sector-Erase */
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out_8(base+0x555, 0x80);
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udelay(1);
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out_8(base+0x555, 0xaa);
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udelay(1);
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out_8(base+0x2aa, 0x55);
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udelay(1);
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out_8(base, 0x30);
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udelay(1);
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
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break;
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}
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stat = in_8(base) ^ in_8(base);
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} while (stat != 0);
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/* Reset */
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out_8(base, 0xf0);
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udelay(1);
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for (i=0; i<NVRAM_SIZE; i++)
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if (base[i] != 0xff) {
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printk(KERN_ERR "nvram: AMD flash erase failed !\n");
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return -ENXIO;
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}
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return 0;
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}
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static int __pmac amd_write_bank(int bank, u8* datas)
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{
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int i, stat = 0;
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unsigned long timeout;
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u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: AMD Writing bank %d...\n", bank);
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for (i=0; i<NVRAM_SIZE; i++) {
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/* Unlock 1 */
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out_8(base+0x555, 0xaa);
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udelay(1);
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/* Unlock 2 */
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out_8(base+0x2aa, 0x55);
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udelay(1);
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/* Write single word */
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out_8(base+0x555, 0xa0);
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udelay(1);
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out_8(base+i, datas[i]);
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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printk(KERN_ERR "nvram: AMD flash write timeout !\n");
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break;
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}
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stat = in_8(base) ^ in_8(base);
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} while (stat != 0);
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if (stat != 0)
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break;
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}
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/* Reset */
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out_8(base, 0xf0);
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udelay(1);
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for (i=0; i<NVRAM_SIZE; i++)
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if (base[i] != datas[i]) {
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printk(KERN_ERR "nvram: AMD flash write failed !\n");
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return -ENXIO;
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}
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return 0;
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}
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static void __init lookup_partitions(void)
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{
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u8 buffer[17];
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int i, offset;
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struct chrp_header* hdr;
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if (pmac_newworld) {
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nvram_partitions[pmac_nvram_OF] = -1;
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nvram_partitions[pmac_nvram_XPRAM] = -1;
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nvram_partitions[pmac_nvram_NR] = -1;
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hdr = (struct chrp_header *)buffer;
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offset = 0;
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buffer[16] = 0;
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do {
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for (i=0;i<16;i++)
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buffer[i] = nvram_read_byte(offset+i);
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if (!strcmp(hdr->name, "common"))
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nvram_partitions[pmac_nvram_OF] = offset + 0x10;
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if (!strcmp(hdr->name, "APL,MacOS75")) {
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nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
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nvram_partitions[pmac_nvram_NR] = offset + 0x110;
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}
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offset += (hdr->len * 0x10);
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} while(offset < NVRAM_SIZE);
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} else {
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nvram_partitions[pmac_nvram_OF] = 0x1800;
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nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
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nvram_partitions[pmac_nvram_NR] = 0x1400;
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}
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DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
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DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
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DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
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}
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static void __pmac core99_nvram_sync(void)
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{
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struct core99_header* hdr99;
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unsigned long flags;
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if (!is_core_99 || !nvram_data || !nvram_image)
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return;
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spin_lock_irqsave(&nv_lock, flags);
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if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
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NVRAM_SIZE))
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goto bail;
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DBG("Updating nvram...\n");
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hdr99 = (struct core99_header*)nvram_image;
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hdr99->generation++;
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hdr99->hdr.signature = CORE99_SIGNATURE;
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hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
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hdr99->adler = core99_calc_adler(nvram_image);
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core99_bank = core99_bank ? 0 : 1;
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if (core99_erase_bank)
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if (core99_erase_bank(core99_bank)) {
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printk("nvram: Error erasing bank %d\n", core99_bank);
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goto bail;
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}
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if (core99_write_bank)
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if (core99_write_bank(core99_bank, nvram_image))
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printk("nvram: Error writing bank %d\n", core99_bank);
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bail:
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spin_unlock_irqrestore(&nv_lock, flags);
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#ifdef DEBUG
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mdelay(2000);
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#endif
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}
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void __init pmac_nvram_init(void)
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{
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struct device_node *dp;
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nvram_naddrs = 0;
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dp = find_devices("nvram");
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if (dp == NULL) {
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printk(KERN_ERR "Can't find NVRAM device\n");
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return;
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}
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nvram_naddrs = dp->n_addrs;
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is_core_99 = device_is_compatible(dp, "nvram,flash");
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if (is_core_99) {
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int i;
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u32 gen_bank0, gen_bank1;
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if (nvram_naddrs < 1) {
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printk(KERN_ERR "nvram: no address\n");
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return;
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}
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nvram_image = alloc_bootmem(NVRAM_SIZE);
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if (nvram_image == NULL) {
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printk(KERN_ERR "nvram: can't allocate ram image\n");
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return;
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}
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nvram_data = ioremap(dp->addrs[0].address, NVRAM_SIZE*2);
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nvram_naddrs = 1; /* Make sure we get the correct case */
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DBG("nvram: Checking bank 0...\n");
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gen_bank0 = core99_check((u8 *)nvram_data);
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gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
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core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
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DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
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DBG("nvram: Active bank is: %d\n", core99_bank);
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for (i=0; i<NVRAM_SIZE; i++)
|
|
nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
|
|
|
|
ppc_md.nvram_read_val = core99_nvram_read_byte;
|
|
ppc_md.nvram_write_val = core99_nvram_write_byte;
|
|
ppc_md.nvram_sync = core99_nvram_sync;
|
|
/*
|
|
* Maybe we could be smarter here though making an exclusive list
|
|
* of known flash chips is a bit nasty as older OF didn't provide us
|
|
* with a useful "compatible" entry. A solution would be to really
|
|
* identify the chip using flash id commands and base ourselves on
|
|
* a list of known chips IDs
|
|
*/
|
|
if (device_is_compatible(dp, "amd-0137")) {
|
|
core99_erase_bank = amd_erase_bank;
|
|
core99_write_bank = amd_write_bank;
|
|
} else {
|
|
core99_erase_bank = sm_erase_bank;
|
|
core99_write_bank = sm_write_bank;
|
|
}
|
|
} else if (_machine == _MACH_chrp && nvram_naddrs == 1) {
|
|
nvram_data = ioremap(dp->addrs[0].address + isa_mem_base,
|
|
dp->addrs[0].size);
|
|
nvram_mult = 1;
|
|
ppc_md.nvram_read_val = direct_nvram_read_byte;
|
|
ppc_md.nvram_write_val = direct_nvram_write_byte;
|
|
} else if (nvram_naddrs == 1) {
|
|
nvram_data = ioremap(dp->addrs[0].address, dp->addrs[0].size);
|
|
nvram_mult = (dp->addrs[0].size + NVRAM_SIZE - 1) / NVRAM_SIZE;
|
|
ppc_md.nvram_read_val = direct_nvram_read_byte;
|
|
ppc_md.nvram_write_val = direct_nvram_write_byte;
|
|
} else if (nvram_naddrs == 2) {
|
|
nvram_addr = ioremap(dp->addrs[0].address, dp->addrs[0].size);
|
|
nvram_data = ioremap(dp->addrs[1].address, dp->addrs[1].size);
|
|
ppc_md.nvram_read_val = indirect_nvram_read_byte;
|
|
ppc_md.nvram_write_val = indirect_nvram_write_byte;
|
|
} else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
|
|
#ifdef CONFIG_ADB_PMU
|
|
nvram_naddrs = -1;
|
|
ppc_md.nvram_read_val = pmu_nvram_read_byte;
|
|
ppc_md.nvram_write_val = pmu_nvram_write_byte;
|
|
#endif /* CONFIG_ADB_PMU */
|
|
} else {
|
|
printk(KERN_ERR "Don't know how to access NVRAM with %d addresses\n",
|
|
nvram_naddrs);
|
|
}
|
|
lookup_partitions();
|
|
}
|
|
|
|
int __pmac pmac_get_partition(int partition)
|
|
{
|
|
return nvram_partitions[partition];
|
|
}
|
|
|
|
u8 __pmac pmac_xpram_read(int xpaddr)
|
|
{
|
|
int offset = nvram_partitions[pmac_nvram_XPRAM];
|
|
|
|
if (offset < 0)
|
|
return 0xff;
|
|
|
|
return ppc_md.nvram_read_val(xpaddr + offset);
|
|
}
|
|
|
|
void __pmac pmac_xpram_write(int xpaddr, u8 data)
|
|
{
|
|
int offset = nvram_partitions[pmac_nvram_XPRAM];
|
|
|
|
if (offset < 0)
|
|
return;
|
|
|
|
ppc_md.nvram_write_val(xpaddr + offset, data);
|
|
}
|
|
|
|
EXPORT_SYMBOL(pmac_get_partition);
|
|
EXPORT_SYMBOL(pmac_xpram_read);
|
|
EXPORT_SYMBOL(pmac_xpram_write);
|