c5f0f83c3b
The AT91RM9200 Ethernet controller still has a fixed IO mapping. So: * Remove the fixed IO mapping and AT91_VA_BASE_EMAC definition. * Pass the physical base-address via platform-resources to the driver. * Convert at91_ether.c driver to perform an ioremap(). * Ethernet PHY detection needs to be performed during the driver initialization process, it can no longer be done first. Signed-off-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
113 lines
3.2 KiB
C
113 lines
3.2 KiB
C
/*
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* Ethernet driver for the Atmel AT91RM9200 (Thunder)
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*
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* Copyright (C) SAN People (Pty) Ltd
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*
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* Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
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* Initial version by Rick Bronson.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef AT91_ETHERNET
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#define AT91_ETHERNET
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/* Davicom 9161 PHY */
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#define MII_DM9161_ID 0x0181b880
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#define MII_DM9161A_ID 0x0181b8a0
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#define MII_DSCR_REG 16
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#define MII_DSCSR_REG 17
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#define MII_DSINTR_REG 21
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/* Intel LXT971A PHY */
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#define MII_LXT971A_ID 0x001378E0
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#define MII_ISINTE_REG 18
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#define MII_ISINTS_REG 19
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#define MII_LEDCTRL_REG 20
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/* Realtek RTL8201 PHY */
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#define MII_RTL8201_ID 0x00008200
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/* Broadcom BCM5221 PHY */
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#define MII_BCM5221_ID 0x004061e0
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#define MII_BCMINTR_REG 26
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/* National Semiconductor DP83847 */
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#define MII_DP83847_ID 0x20005c30
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/* National Semiconductor DP83848 */
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#define MII_DP83848_ID 0x20005c90
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#define MII_DPPHYSTS_REG 16
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#define MII_DPMICR_REG 17
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#define MII_DPMISR_REG 18
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/* Altima AC101L PHY */
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#define MII_AC101L_ID 0x00225520
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/* Micrel KS8721 PHY */
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#define MII_KS8721_ID 0x00221610
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/* Teridian 78Q2123/78Q2133 */
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#define MII_T78Q21x3_ID 0x000e7230
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#define MII_T78Q21INT_REG 17
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/* SMSC LAN83C185 */
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#define MII_LAN83C185_ID 0x0007C0A0
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/* ........................................................................ */
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#define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */
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#define MAX_RX_DESCR 9 /* max number of receive buffers */
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#define EMAC_DESC_DONE 0x00000001 /* bit for if DMA is done */
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#define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */
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#define EMAC_BROADCAST 0x80000000 /* broadcast address */
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#define EMAC_MULTICAST 0x40000000 /* multicast address */
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#define EMAC_UNICAST 0x20000000 /* unicast address */
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struct rbf_t
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{
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unsigned int addr;
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unsigned long size;
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};
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struct recv_desc_bufs
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{
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struct rbf_t descriptors[MAX_RX_DESCR]; /* must be on sizeof (rbf_t) boundary */
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char recv_buf[MAX_RX_DESCR][MAX_RBUFF_SZ]; /* must be on long boundary */
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};
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struct at91_private
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{
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struct mii_if_info mii; /* ethtool support */
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struct macb_platform_data board_data; /* board-specific
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* configuration (shared with
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* macb for common data */
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void __iomem *emac_base; /* base register address */
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struct clk *ether_clk; /* clock */
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/* PHY */
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unsigned long phy_type; /* type of PHY (PHY_ID) */
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spinlock_t lock; /* lock for MDI interface */
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short phy_media; /* media interface type */
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unsigned short phy_address; /* 5-bit MDI address of PHY (0..31) */
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struct timer_list check_timer; /* Poll link status */
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/* Transmit */
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struct sk_buff *skb; /* holds skb until xmit interrupt completes */
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dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
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int skb_length; /* saved skb length for pci_unmap_single */
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/* Receive */
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int rxBuffIndex; /* index into receive descriptor list */
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struct recv_desc_bufs *dlist; /* descriptor list address */
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struct recv_desc_bufs *dlist_phys; /* descriptor list physical address */
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};
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#endif
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