Andre Schwarz 6eb9d32298 powerpc/mpc5200: PCI write combine timer ... On MPC5200 the PCI target control register (PCITCR) @ MBAR + 0xD6C is initialized with only bit 7 (Latrule disable) set. The 8-Bit write combine timer (Bits 24..31) should be also set to a reasonable value _greater zero_ (0x08 = default) since setting it to 0x00 leads to _very poor_ performance as a PCI target since external burst won't be possible at all. Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>		2008-07-12 12:10:12 -06:00
..
efika.c	[POWERPC] Add common clock setting routine mpc52xx_psc_set_clkdiv()	2008-01-26 15:32:18 -07:00
Kconfig	[POWERPC] mpc5200: add gpiolib support for mpc5200	2008-04-29 07:16:59 -06:00
lite5200_pm.c	Suspend: Introduce begin() and end() callbacks	2008-02-01 18:30:56 -05:00
lite5200_sleep.S
lite5200.c	[POWERPC] Replace remaining __FUNCTION__ occurrences	2008-04-01 20:43:09 +11:00
Makefile	[POWERPC] mpc5200: add gpiolib support for mpc5200	2008-04-29 07:16:59 -06:00
mpc52xx_common.c	[POWERPC] Add export for mpc52xx_set_psc_clkdiv	2008-02-23 22:51:28 -07:00
mpc52xx_gpio.c	mpc52xx_gpio iomem annotations	2008-06-04 08:06:02 -07:00
mpc52xx_pci.c	powerpc/mpc5200: PCI write combine timer	2008-07-12 12:10:12 -06:00
mpc52xx_pic.c	[POWERPC] mpc5200: add interrupt type function	2008-04-29 07:16:35 -06:00
mpc52xx_pic.h
mpc52xx_pm.c	[POWERPC] mpc5200: normalize compatible property bindings	2008-01-26 15:26:01 -07:00
mpc52xx_sleep.S
mpc5200_simple.c	[POWERPC] mpc5200: add Phytec pcm030 board support	2008-04-29 07:17:12 -06:00