49cbe78637
"""The Marvell® PXA168 processor is the first in a family of application processors targeted at mass market opportunities in computing and consumer devices. It balances high computing and multimedia performance with low power consumption to support extended battery life, and includes a wealth of integrated peripherals to reduce overall BOM cost .... """ See http://www.marvell.com/featured/pxa168.jsp for more information. 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core, there are many enhancements like instructions for flushing the whole D-cache, and so on 2. Clock reuses Russell's common clkdev, and added the basic support for UART1/2. 3. Devices are a bit different from the 'mach-pxa' way, the platform devices are now dynamically allocated only when necessary (i.e. when pxa_register_device() is called). Description for each device are stored in an array of 'struct pxa_device_desc'. Now that: a. this array of device description is marked with __initdata and can be freed up system is fully up b. which means board code has to add all needed devices early in his initializing function c. platform specific data can now be marked as __initdata since they are allocated and copied by platform_device_add_data() 4. only the basic UART1/2/3 are added, more devices will come later. Signed-off-by: Jason Chagas <chagas@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
72 lines
1.7 KiB
C
72 lines
1.7 KiB
C
/*
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* linux/arch/arm/mach-mmp/clock.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <asm/clkdev.h>
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struct clkops {
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void (*enable)(struct clk *);
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void (*disable)(struct clk *);
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unsigned long (*getrate)(struct clk *);
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};
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struct clk {
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const struct clkops *ops;
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void __iomem *clk_rst; /* clock reset control register */
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int fnclksel; /* functional clock select (APBC) */
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uint32_t enable_val; /* value for clock enable (APMU) */
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unsigned long rate;
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int enabled;
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};
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extern struct clkops apbc_clk_ops;
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#define APBC_CLK(_name, _reg, _fnclksel, _rate) \
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struct clk clk_##_name = { \
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.clk_rst = (void __iomem *)APBC_##_reg, \
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.fnclksel = _fnclksel, \
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.rate = _rate, \
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.ops = &apbc_clk_ops, \
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}
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#define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \
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struct clk clk_##_name = { \
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.clk_rst = (void __iomem *)APBC_##_reg, \
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.fnclksel = _fnclksel, \
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.rate = _rate, \
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.ops = _ops, \
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}
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#define APMU_CLK(_name, _reg, _eval, _rate) \
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struct clk clk_##_name = { \
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.clk_rst = (void __iomem *)APMU_##_reg, \
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.enable_val = _eval, \
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.rate = _rate, \
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.ops = &apmu_clk_ops, \
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}
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#define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \
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struct clk clk_##_name = { \
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.clk_rst = (void __iomem *)APMU_##_reg, \
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.enable_val = _eval, \
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.rate = _rate, \
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.ops = _ops, \
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}
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#define INIT_CLKREG(_clk, _devname, _conname) \
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{ \
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.clk = _clk, \
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.dev_id = _devname, \
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.con_id = _conname, \
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}
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extern struct clk clk_pxa168_gpio;
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extern struct clk clk_pxa168_timers;
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extern void clks_register(struct clk_lookup *, size_t);
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