cee8113a29
Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 lines
74 B
Makefile
3 lines
74 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_XILINX_VCU) += xlnx_vcu.o
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