5761d64b27
The commits: commit37a47db8d7Author: Balaji Rao <balajirrao@gmail.com> Date: Wed Jan 30 13:30:03 2008 +0100 x86: assign IRQs to HPET timers, fix and commite3f37a54f6Author: Balaji Rao <balajirrao@gmail.com> Date: Wed Jan 30 13:30:03 2008 +0100 x86: assign IRQs to HPET timers have been identified to cause a regression on some platforms due to the assignement of legacy IRQs which makes the legacy devices connected to those IRQs disfunctional. Revert them. This fixes http://bugzilla.kernel.org/show_bug.cgi?id=10382 Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
138 lines
3.2 KiB
C
138 lines
3.2 KiB
C
#ifndef __HPET__
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#define __HPET__ 1
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#include <linux/compiler.h>
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#ifdef __KERNEL__
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/*
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* Offsets into HPET Registers
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*/
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struct hpet {
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u64 hpet_cap; /* capabilities */
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u64 res0; /* reserved */
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u64 hpet_config; /* configuration */
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u64 res1; /* reserved */
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u64 hpet_isr; /* interrupt status reg */
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u64 res2[25]; /* reserved */
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union { /* main counter */
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u64 _hpet_mc64;
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u32 _hpet_mc32;
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unsigned long _hpet_mc;
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} _u0;
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u64 res3; /* reserved */
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struct hpet_timer {
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u64 hpet_config; /* configuration/cap */
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union { /* timer compare register */
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u64 _hpet_hc64;
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u32 _hpet_hc32;
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unsigned long _hpet_compare;
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} _u1;
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u64 hpet_fsb[2]; /* FSB route */
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} hpet_timers[1];
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};
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#define hpet_mc _u0._hpet_mc
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#define hpet_compare _u1._hpet_compare
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#define HPET_MAX_TIMERS (32)
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/*
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* HPET general capabilities register
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*/
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#define HPET_COUNTER_CLK_PERIOD_MASK (0xffffffff00000000ULL)
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#define HPET_COUNTER_CLK_PERIOD_SHIFT (32UL)
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#define HPET_VENDOR_ID_MASK (0x00000000ffff0000ULL)
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#define HPET_VENDOR_ID_SHIFT (16ULL)
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#define HPET_LEG_RT_CAP_MASK (0x8000)
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#define HPET_COUNTER_SIZE_MASK (0x2000)
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#define HPET_NUM_TIM_CAP_MASK (0x1f00)
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#define HPET_NUM_TIM_CAP_SHIFT (8ULL)
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/*
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* HPET general configuration register
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*/
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#define HPET_LEG_RT_CNF_MASK (2UL)
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#define HPET_ENABLE_CNF_MASK (1UL)
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/*
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* Timer configuration register
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*/
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#define Tn_INT_ROUTE_CAP_MASK (0xffffffff00000000ULL)
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#define Tn_INI_ROUTE_CAP_SHIFT (32UL)
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#define Tn_FSB_INT_DELCAP_MASK (0x8000UL)
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#define Tn_FSB_INT_DELCAP_SHIFT (15)
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#define Tn_FSB_EN_CNF_MASK (0x4000UL)
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#define Tn_FSB_EN_CNF_SHIFT (14)
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#define Tn_INT_ROUTE_CNF_MASK (0x3e00UL)
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#define Tn_INT_ROUTE_CNF_SHIFT (9)
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#define Tn_32MODE_CNF_MASK (0x0100UL)
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#define Tn_VAL_SET_CNF_MASK (0x0040UL)
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#define Tn_SIZE_CAP_MASK (0x0020UL)
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#define Tn_PER_INT_CAP_MASK (0x0010UL)
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#define Tn_TYPE_CNF_MASK (0x0008UL)
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#define Tn_INT_ENB_CNF_MASK (0x0004UL)
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#define Tn_INT_TYPE_CNF_MASK (0x0002UL)
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/*
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* Timer FSB Interrupt Route Register
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*/
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#define Tn_FSB_INT_ADDR_MASK (0xffffffff00000000ULL)
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#define Tn_FSB_INT_ADDR_SHIFT (32UL)
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#define Tn_FSB_INT_VAL_MASK (0x00000000ffffffffULL)
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/*
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* exported interfaces
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*/
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struct hpet_task {
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void (*ht_func) (void *);
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void *ht_data;
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void *ht_opaque;
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};
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struct hpet_data {
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unsigned long hd_phys_address;
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void __iomem *hd_address;
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unsigned short hd_nirqs;
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unsigned short hd_flags;
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unsigned int hd_state; /* timer allocated */
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unsigned int hd_irq[HPET_MAX_TIMERS];
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};
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#define HPET_DATA_PLATFORM 0x0001 /* platform call to hpet_alloc */
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static inline void hpet_reserve_timer(struct hpet_data *hd, int timer)
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{
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hd->hd_state |= (1 << timer);
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return;
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}
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int hpet_alloc(struct hpet_data *);
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#endif /* __KERNEL__ */
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struct hpet_info {
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unsigned long hi_ireqfreq; /* Hz */
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unsigned long hi_flags; /* information */
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unsigned short hi_hpet;
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unsigned short hi_timer;
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};
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#define HPET_INFO_PERIODIC 0x0001 /* timer is periodic */
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#define HPET_IE_ON _IO('h', 0x01) /* interrupt on */
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#define HPET_IE_OFF _IO('h', 0x02) /* interrupt off */
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#define HPET_INFO _IOR('h', 0x03, struct hpet_info)
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#define HPET_EPI _IO('h', 0x04) /* enable periodic */
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#define HPET_DPI _IO('h', 0x05) /* disable periodic */
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#define HPET_IRQFREQ _IOW('h', 0x6, unsigned long) /* IRQFREQ usec */
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#endif /* !__HPET__ */
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