0f22aab897
This driver is for the Airgo AGNX00 wireless chip. From: Li YanBo <dreamfly281@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
251 lines
7.2 KiB
C
251 lines
7.2 KiB
C
#ifndef AGNX_XMIT_H_
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#define AGNX_XMIT_H_
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#include <net/mac80211.h>
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struct agnx_priv;
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static inline u32 agnx_set_bits(u32 mask, u8 shift, u32 value)
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{
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return (value << shift) & mask;
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}
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static inline u32 agnx_get_bits(u32 mask, u8 shift, u32 value)
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{
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return (value & mask) >> shift;
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}
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struct agnx_rx {
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__be16 rx_packet_duration; /* RX Packet Duration */
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__be16 replay_cnt; /* Replay Count */
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} __attribute__((__packed__));
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struct agnx_tx {
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u8 long_retry_limit; /* Long Retry Limit */
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u8 short_retry_limit; /* Short Retry Limit */
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u8 long_retry_cnt; /* Long Retry Count */
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u8 short_retry_cnt; /* Short Retry Count */
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} __attribute__((__packed__));
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/* Copy from bcm43xx */
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#define P4D_BYT3S(magic, nr_bytes) u8 __p4dding##magic[nr_bytes]
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#define P4D_BYTES(line, nr_bytes) P4D_BYT3S(line, nr_bytes)
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#define PAD_BYTES(nr_bytes) P4D_BYTES(__LINE__, nr_bytes)
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#define P4D_BIT3S(magic, nr_bits) __be32 __padding##magic:nr_bits
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#define P4D_BITS(line, nr_bits) P4D_BIT3S(line, nr_bits)
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#define PAD_BITS(nr_bits) P4D_BITS(__LINE__, nr_bits)
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struct agnx_hdr {
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__be32 reg0;
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#define RTS 0x80000000 /* RTS */
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#define RTS_SHIFT 31
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#define MULTICAST 0x40000000 /* multicast */
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#define MULTICAST_SHIFT 30
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#define ACK 0x30000000 /* ACK */
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#define ACK_SHIFT 28
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#define TM 0x08000000 /* TM */
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#define TM_SHIFT 27
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#define RELAY 0x04000000 /* Relay */
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#define RELAY_SHIFT 26
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/* PAD_BITS(4); */
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#define REVISED_FCS 0x00380000 /* revised FCS */
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#define REVISED_FCS_SHIFT 19
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#define NEXT_BUFFER_ADDR 0x0007FFFF /* Next Buffer Address */
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#define NEXT_BUFFER_ADDR_SHIFT 0
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__be32 reg1;
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#define MAC_HDR_LEN 0xFC000000 /* MAC Header Length */
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#define MAC_HDR_LEN_SHIFT 26
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#define DURATION_OVERIDE 0x02000000 /* Duration Override */
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#define DURATION_OVERIDE_SHIFT 25
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#define PHY_HDR_OVERIDE 0x01000000 /* PHY Header Override */
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#define PHY_HDR_OVERIDE_SHIFT 24
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#define CRC_FAIL 0x00800000 /* CRC fail */
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#define CRC_FAIL_SHIFT 23
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/* PAD_BITS(1); */
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#define SEQUENCE_NUMBER 0x00200000 /* Sequence Number */
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#define SEQUENCE_NUMBER_SHIFT 21
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/* PAD_BITS(2); */
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#define BUFF_HEAD_ADDR 0x0007FFFF /* Buffer Head Address */
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#define BUFF_HEAD_ADDR_SHIFT 0
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__be32 reg2;
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#define PDU_COUNT 0xFC000000 /* PDU Count */
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#define PDU_COUNT_SHIFT 26
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/* PAD_BITS(3); */
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#define WEP_KEY 0x00600000 /* WEP Key # */
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#define WEP_KEY_SHIFT 21
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#define USES_WEP_KEY 0x00100000 /* Uses WEP Key */
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#define USES_WEP_KEY_SHIFT 20
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#define KEEP_ALIVE 0x00080000 /* Keep alive */
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#define KEEP_ALIVE_SHIFT 19
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#define BUFF_TAIL_ADDR 0x0007FFFF /* Buffer Tail Address */
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#define BUFF_TAIL_ADDR_SHIFT 0
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__be32 reg3;
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#define CTS_11G 0x80000000 /* CTS in 11g */
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#define CTS_11G_SHIFT 31
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#define RTS_11G 0x40000000 /* RTS in 11g */
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#define RTS_11G_SHIFT 30
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/* PAD_BITS(2); */
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#define FRAG_SIZE 0x0FFF0000 /* fragment size */
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#define FRAG_SIZE_SHIFT 16
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#define PAYLOAD_LEN 0x0000FFF0 /* payload length */
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#define PAYLOAD_LEN_SHIFT 4
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#define FRAG_NUM 0x0000000F /* number of frags */
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#define FRAG_NUM_SHIFT 0
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__be32 reg4;
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/* PAD_BITS(4); */
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#define RELAY_STAID 0x0FFF0000 /* relayStald */
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#define RELAY_STAID_SHIFT 16
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#define STATION_ID 0x0000FFF0 /* Station ID */
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#define STATION_ID_SHIFT 4
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#define WORKQUEUE_ID 0x0000000F /* Workqueue ID */
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#define WORKQUEUE_ID_SHIFT 0
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/* FIXME this register maybe is LE? */
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__be32 reg5;
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/* PAD_BITS(4); */
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#define ROUTE_HOST 0x0F000000
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#define ROUTE_HOST_SHIFT 24
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#define ROUTE_CARD_CPU 0x00F00000
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#define ROUTE_CARD_CPU_SHIFT 20
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#define ROUTE_ENCRYPTION 0x000F0000
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#define ROUTE_ENCRYPTION_SHIFT 16
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#define ROUTE_TX 0x0000F000
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#define ROUTE_TX_SHIFT 12
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#define ROUTE_RX1 0x00000F00
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#define ROUTE_RX1_SHIFT 8
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#define ROUTE_RX2 0x000000F0
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#define ROUTE_RX2_SHIFT 4
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#define ROUTE_COMPRESSION 0x0000000F
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#define ROUTE_COMPRESSION_SHIFT 0
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__be32 _11g0; /* 11g */
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__be32 _11g1; /* 11g */
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__be32 _11b0; /* 11b */
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__be32 _11b1; /* 11b */
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u8 mac_hdr[32]; /* MAC header */
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__be16 rts_duration; /* RTS duration */
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__be16 last_duration; /* Last duration */
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__be16 sec_last_duration; /* Second to Last duration */
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__be16 other_duration; /* Other duration */
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__be16 tx_last_duration; /* TX Last duration */
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__be16 tx_other_duration; /* TX Other Duration */
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__be16 last_11g_len; /* Length of last 11g */
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__be16 other_11g_len; /* Lenght of other 11g */
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__be16 last_11b_len; /* Length of last 11b */
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__be16 other_11b_len; /* Lenght of other 11b */
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__be16 reg6;
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#define MBF 0xF000 /* mbf */
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#define MBF_SHIFT 12
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#define RSVD4 0x0FFF /* rsvd4 */
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#define RSVD4_SHIFT 0
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__be16 rx_frag_stat; /* RX fragmentation status */
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__be32 time_stamp; /* TimeStamp */
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__be32 phy_stats_hi; /* PHY stats hi */
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__be32 phy_stats_lo; /* PHY stats lo */
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__be32 mic_key0; /* MIC key 0 */
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__be32 mic_key1; /* MIC key 1 */
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union { /* RX/TX Union */
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struct agnx_rx rx;
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struct agnx_tx tx;
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};
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u8 rx_channel; /* Recieve Channel */
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PAD_BYTES(3);
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u8 reserved[4];
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} __attribute__((__packed__));
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struct agnx_desc {
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#define PACKET_LEN 0xFFF00000
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#define PACKET_LEN_SHIFT 20
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/* ------------------------------------------------ */
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#define FIRST_PACKET_MASK 0x00080000
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#define FIRST_PACKET_MASK_SHIFT 19
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#define FIRST_RESERV2 0x00040000
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#define FIRST_RESERV2_SHIFT 18
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#define FIRST_TKIP_ERROR 0x00020000
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#define FIRST_TKIP_ERROR_SHIFT 17
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#define FIRST_TKIP_PACKET 0x00010000
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#define FIRST_TKIP_PACKET_SHIFT 16
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#define FIRST_RESERV1 0x0000F000
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#define FIRST_RESERV1_SHIFT 12
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#define FIRST_FRAG_LEN 0x00000FF8
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#define FIRST_FRAG_LEN_SHIFT 3
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/* ------------------------------------------------ */
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#define SUB_RESERV2 0x000c0000
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#define SUB_RESERV2_SHIFT 18
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#define SUB_TKIP_ERROR 0x00020000
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#define SUB_TKIP_ERROR_SHIFT 17
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#define SUB_TKIP_PACKET 0x00010000
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#define SUB_TKIP_PACKET_SHIFT 16
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#define SUB_RESERV1 0x00008000
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#define SUB_RESERV1_SHIFT 15
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#define SUB_FRAG_LEN 0x00007FF8
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#define SUB_FRAG_LEN_SHIFT 3
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/* ------------------------------------------------ */
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#define FIRST_FRAG 0x00000004
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#define FIRST_FRAG_SHIFT 2
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#define LAST_FRAG 0x00000002
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#define LAST_FRAG_SHIFT 1
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#define OWNER 0x00000001
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#define OWNER_SHIFT 0
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__be32 frag;
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__be32 dma_addr;
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} __attribute__((__packed__));
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enum {HEADER, PACKET};
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struct agnx_info {
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struct sk_buff *skb;
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dma_addr_t mapping;
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u32 dma_len; /* dma buffer len */
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/* Below fields only usful for tx */
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u32 hdr_len; /* ieee80211 header length */
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unsigned int type;
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struct ieee80211_tx_info *txi;
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struct ieee80211_hdr hdr;
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};
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struct agnx_ring {
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struct agnx_desc *desc;
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dma_addr_t dma;
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struct agnx_info *info;
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/* Will lead to overflow when sent packet number enough? */
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unsigned int idx;
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unsigned int idx_sent; /* only usful for txd and txm */
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unsigned int size;
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};
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#define AGNX_RX_RING_SIZE 128
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#define AGNX_TXD_RING_SIZE 256
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#define AGNX_TXM_RING_SIZE 128
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void disable_rx_interrupt(struct agnx_priv *priv);
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void enable_rx_interrupt(struct agnx_priv *priv);
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int fill_rings(struct agnx_priv *priv);
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void unfill_rings(struct agnx_priv *priv);
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void handle_rx_irq(struct agnx_priv *priv);
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void handle_txd_irq(struct agnx_priv *priv);
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void handle_txm_irq(struct agnx_priv *priv);
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void handle_other_irq(struct agnx_priv *priv);
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int _agnx_tx(struct agnx_priv *priv, struct sk_buff *skb);
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#endif /* AGNX_XMIT_H_ */
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