3cd9e19ebc
The merge of sparsemem broke ARM discontigmem. Fix it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
75 lines
1.8 KiB
Plaintext
75 lines
1.8 KiB
Plaintext
if ARCH_CLPS711X
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menu "CLPS711X/EP721X Implementations"
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config ARCH_AUTCPU12
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bool "AUTCPU12"
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help
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Say Y if you intend to run the kernel on the autronix autcpu12
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board. This board is based on a Cirrus Logic CS89712.
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config ARCH_CDB89712
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bool "CDB89712"
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select ISA
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help
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This is an evaluation board from Cirrus for the CS89712 processor.
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The board includes 2 serial ports, Ethernet, IRDA, and expansion
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headers. It comes with 16 MB SDRAM and 8 MB flash ROM.
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config ARCH_CEIVA
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bool "CEIVA"
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help
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Say Y here if you intend to run this kernel on the Ceiva/Polaroid
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PhotoMax Digital Picture Frame.
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config ARCH_CLEP7312
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bool "CLEP7312"
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config ARCH_EDB7211
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bool "EDB7211"
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select ISA
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select ARCH_DISCONTIGMEM_ENABLE
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help
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Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
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evaluation board.
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config ARCH_P720T
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bool "P720T"
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help
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Say Y here if you intend to run this kernel on the ARM Prospector
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720T.
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config ARCH_FORTUNET
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bool "FORTUNET"
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# XXX Maybe these should indicate register compatibility
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# instead of being mutually exclusive.
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config ARCH_EP7211
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bool
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depends on ARCH_EDB7211
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default y
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config ARCH_EP7212
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bool
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depends on ARCH_P720T || ARCH_CEIVA
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default y
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config EP72XX_ROM_BOOT
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bool "EP72xx ROM boot"
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depends on ARCH_EP7211 || ARCH_EP7212
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---help---
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If you say Y here, your CLPS711x-based kernel will use the bootstrap
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mode memory map instead of the normal memory map.
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Processors derived from the Cirrus CLPS-711X core support two boot
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modes. Normal mode boots from the external memory device at CS0.
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Bootstrap mode rearranges parts of the memory map, placing an
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internal 128 byte bootstrap ROM at CS0. This option performs the
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address map changes required to support booting in this mode.
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You almost surely want to say N here.
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endmenu
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endif
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