6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
236 lines
8.2 KiB
C
236 lines
8.2 KiB
C
/*
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* Author: Armin Kuster <akuster@mvista.com>
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*
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* 2001 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_IBMSTB4_H__
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#define __ASM_IBMSTB4_H__
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/* serial port defines */
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#define STB04xxx_IO_BASE ((uint)0xe0000000)
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#define PPC4xx_PCI_IO_ADDR STB04xxx_IO_BASE
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#define PPC4xx_ONB_IO_PADDR STB04xxx_IO_BASE
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#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000)
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#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024)
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/*
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* map STB04xxx internal i/o address (0x400x00xx) to an address
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* which is below the 2GB limit...
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*
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* 4000 000x uart1 -> 0xe000 000x
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* 4001 00xx ppu
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* 4002 00xx smart card
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* 4003 000x iic
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* 4004 000x uart0
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* 4005 0xxx timer
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* 4006 00xx gpio
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* 4007 00xx smart card
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* 400b 000x iic
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* 400c 000x scp
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* 400d 000x modem
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* 400e 000x uart2
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*/
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#define STB04xxx_MAP_IO_ADDR(a) (((uint)(a)) + (STB04xxx_IO_BASE - 0x40000000))
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#define RS_TABLE_SIZE 3
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#define UART0_INT 20
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#ifdef __BOOTER__
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#define UART0_IO_BASE 0x40040000
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#else
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#define UART0_IO_BASE 0xe0040000
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#endif
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#define UART1_INT 21
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#ifdef __BOOTER__
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#define UART1_IO_BASE 0x40000000
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#else
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#define UART1_IO_BASE 0xe0000000
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#endif
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#define UART2_INT 31
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#ifdef __BOOTER__
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#define UART2_IO_BASE 0x400e0000
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#else
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#define UART2_IO_BASE 0xe00e0000
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#endif
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#define IDE0_BASE 0x400F0000
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#define IDE0_SIZE 0x200
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#define IDE0_IRQ 25
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#define IIC0_BASE 0x40030000
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#define IIC1_BASE 0x400b0000
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#define OPB0_BASE 0x40000000
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#define GPIO0_BASE 0x40060000
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#define USB0_BASE 0x40010000
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#define USB0_SIZE 0xA0
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#define USB0_IRQ 18
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#define IIC_NUMS 2
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#define UART_NUMS 3
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#define IIC0_IRQ 9
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#define IIC1_IRQ 10
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#define IIC_OWN 0x55
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#define IIC_CLOCK 50
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#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
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#define STD_UART_OP(num) \
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{ 0, BASE_BAUD, 0, UART##num##_INT, \
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(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
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iomem_base: (u8 *)UART##num##_IO_BASE, \
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io_type: SERIAL_IO_MEM},
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#if defined(CONFIG_UART0_TTYS0)
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#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
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#define SERIAL_PORT_DFNS \
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STD_UART_OP(0) \
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STD_UART_OP(1) \
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STD_UART_OP(2)
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#endif
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#if defined(CONFIG_UART0_TTYS1)
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#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
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#define SERIAL_PORT_DFNS \
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STD_UART_OP(1) \
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STD_UART_OP(0) \
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STD_UART_OP(2)
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#endif
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#if defined(CONFIG_UART0_TTYS2)
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#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
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#define SERIAL_PORT_DFNS \
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STD_UART_OP(2) \
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STD_UART_OP(0) \
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STD_UART_OP(1)
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#endif
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#define DCRN_BE_BASE 0x090
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#define DCRN_DMA0_BASE 0x0C0
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#define DCRN_DMA1_BASE 0x0C8
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#define DCRN_DMA2_BASE 0x0D0
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#define DCRN_DMA3_BASE 0x0D8
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#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
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#define DCRN_DMASR_BASE 0x0E0
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#define DCRN_PLB0_BASE 0x054
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#define DCRN_PLB1_BASE 0x064
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#define DCRN_POB0_BASE 0x0B0
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#define DCRN_SCCR_BASE 0x120
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#define DCRN_UIC0_BASE 0x040
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#define DCRN_BE_BASE 0x090
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#define DCRN_DMA0_BASE 0x0C0
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#define DCRN_DMA1_BASE 0x0C8
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#define DCRN_DMA2_BASE 0x0D0
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#define DCRN_DMA3_BASE 0x0D8
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#define DCRN_CIC_BASE 0x030
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#define DCRN_DMASR_BASE 0x0E0
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#define DCRN_EBIMC_BASE 0x070
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#define DCRN_DCRX_BASE 0x020
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#define DCRN_CPMFR_BASE 0x102
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#define DCRN_SCCR_BASE 0x120
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#define UIC0 DCRN_UIC0_BASE
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#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */
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#define IBM_CPM_USB0 0x40000000 /* IEEE-1284 */
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#define IBM_CPM_IIC1 0x20000000 /* IIC 1 interface */
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#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */
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#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */
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#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */
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#define IBM_CPM_SDRAM1 0x02000000 /* SDRAM 1 memory controller */
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#define IBM_CPM_DMA 0x01000000 /* DMA controller */
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#define IBM_CPM_DMA1 0x00800000 /* reserved */
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#define IBM_CPM_XPT1 0x00400000 /* reserved */
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#define IBM_CPM_XPT2 0x00200000 /* reserved */
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#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */
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#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */
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#define IBM_CPM_EPI 0x00040000 /* DCR Extension */
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#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */
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#define IBM_CPM_VID 0x00010000 /* reserved */
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#define IBM_CPM_SC1 0x00008000 /* Smart Card 1 */
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#define IBM_CPM_USBSDRA 0x00004000 /* SDRAM 0 memory controller */
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#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */
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#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */
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#define IBM_CPM_GPT 0x00000800 /* GPTPWM */
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#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */
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#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */
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#define IBM_CPM_TMRCLK 0x00000100 /* CPU timers */
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#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */
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#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */
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#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */
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#define IBM_CPM_UART2 0x00000008 /* Serial Control Port */
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#define IBM_CPM_DDIO 0x00000004 /* Descrambler */
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#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */
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#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \
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| IBM_CPM_DMA | IBM_CPM_DMA1 | IBM_CPM_CBS \
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| IBM_CPM_USBSDRA | IBM_CPM_XPT0 | IBM_CPM_TMRCLK \
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| IBM_CPM_XPT27 | IBM_CPM_UIC )
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#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
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#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
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/* DCRN_BESR */
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#define BESR_DSES 0x80000000 /* Data-Side Error Status */
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#define BESR_DMES 0x40000000 /* DMA Error Status */
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#define BESR_RWS 0x20000000 /* Read/Write Status */
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#define BESR_ETMASK 0x1C000000 /* Error Type */
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#define ET_PROT 0
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#define ET_PARITY 1
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#define ET_NCFG 2
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#define ET_BUSERR 4
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#define ET_BUSTO 6
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#define CHR1_CETE 0x00800000 /* CPU external timer enable */
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#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
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#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
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#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
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#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
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#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
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#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
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#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
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#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
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#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
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#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
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#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
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#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
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#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
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#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
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#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
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#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
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#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
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#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
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#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
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#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
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#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
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#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
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#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
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#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
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#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
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#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
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#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */
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#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */
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#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */
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#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */
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#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */
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#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */
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#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */
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#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */
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#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */
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#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */
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#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */
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#include <asm/ibm405.h>
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#endif /* __ASM_IBMSTB4_H__ */
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#endif /* __KERNEL__ */
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