54e269ead6
Patch from Deepak Saxena The expansion bus on the IXP46x NPU can be configured for either 32MiB or 16MiB windows and changing the configuration causes the base address for each chip select for each region to change. Because of this, we cannot hardcode the physical base as we currently do. This patch checks the expansion bus configuration registers at runtime to determine the appropriate window size. Note that this requires that the bootloader already configured the device sizes appropriately, but I feel that is valid assumption to make as the bootloader must configure and access the flash window, the output display (LCD, LEDs, etc) window, and other expansion bus devices. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
94 lines
2.2 KiB
C
94 lines
2.2 KiB
C
/*
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* include/asm-arm/arch-ixp4xx/nslu2.h
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*
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* NSLU2 platform specific definitions
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*
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* Author: Mark Rakes <mrakes AT mac.com>
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* Maintainers: http://www.nslu2-linux.org
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*
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* based on ixdp425.h:
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* Copyright 2004 (c) MontaVista, Software, Inc.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H__
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#error "Do not include this directly, instead #include <asm/hardware.h>"
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#endif
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#define NSLU2_SDA_PIN 7
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#define NSLU2_SCL_PIN 6
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/*
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* NSLU2 PCI IRQs
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*/
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#define NSLU2_PCI_MAX_DEV 3
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#define NSLU2_PCI_IRQ_LINES 3
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/* PCI controller GPIO to IRQ pin mappings */
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#define NSLU2_PCI_INTA_PIN 11
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#define NSLU2_PCI_INTB_PIN 10
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#define NSLU2_PCI_INTC_PIN 9
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#define NSLU2_PCI_INTD_PIN 8
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/* NSLU2 Timer */
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#define NSLU2_FREQ 66000000
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#define NSLU2_CLOCK_TICK_RATE (((NSLU2_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
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#define NSLU2_CLOCK_TICKS_PER_USEC ((NSLU2_CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
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/* GPIO */
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#define NSLU2_GPIO0 0
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#define NSLU2_GPIO1 1
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#define NSLU2_GPIO2 2
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#define NSLU2_GPIO3 3
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#define NSLU2_GPIO4 4
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#define NSLU2_GPIO5 5
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#define NSLU2_GPIO6 6
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#define NSLU2_GPIO7 7
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#define NSLU2_GPIO8 8
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#define NSLU2_GPIO9 9
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#define NSLU2_GPIO10 10
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#define NSLU2_GPIO11 11
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#define NSLU2_GPIO12 12
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#define NSLU2_GPIO13 13
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#define NSLU2_GPIO14 14
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#define NSLU2_GPIO15 15
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/* Buttons */
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#define NSLU2_PB_GPIO NSLU2_GPIO5
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#define NSLU2_PO_GPIO NSLU2_GPIO8 /* power off */
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#define NSLU2_RB_GPIO NSLU2_GPIO12
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#define NSLU2_PB_IRQ IRQ_IXP4XX_GPIO5
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#define NSLU2_RB_IRQ IRQ_IXP4XX_GPIO12
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#define NSLU2_PB_BM (1L << NSLU2_PB_GPIO)
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#define NSLU2_PO_BM (1L << NSLU2_PO_GPIO)
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#define NSLU2_RB_BM (1L << NSLU2_RB_GPIO)
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/* Buzzer */
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#define NSLU2_GPIO_BUZZ 4
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#define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ)
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/* LEDs */
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#define NSLU2_LED_RED NSLU2_GPIO0
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#define NSLU2_LED_GRN NSLU2_GPIO1
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#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED)
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#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN)
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#define NSLU2_LED_DISK1 NSLU2_GPIO2
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#define NSLU2_LED_DISK2 NSLU2_GPIO3
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#define NSLU2_LED_DISK1_BM (1L << NSLU2_GPIO2)
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#define NSLU2_LED_DISK2_BM (1L << NSLU2_GPIO3)
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