61b1a94254
This patch slightly change the TLB flush batch mecanism so that we store the full vaddr (including vsid) when adding an entry to the batch so that the flush part doesn't have to get to the context. This cleans it a bit, and paves the way to future updates like dynamic vsids. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
449 lines
10 KiB
C
449 lines
10 KiB
C
/*
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* native hashtable management.
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*
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* SMP scalability work:
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* Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/spinlock.h>
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#include <linux/bitops.h>
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#include <linux/threads.h>
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#include <linux/smp.h>
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#include <asm/abs_addr.h>
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#include <asm/machdep.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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#include <asm/tlb.h>
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#include <asm/cputable.h>
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#define HPTE_LOCK_BIT 3
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static DEFINE_SPINLOCK(native_tlbie_lock);
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static inline void native_lock_hpte(hpte_t *hptep)
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{
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unsigned long *word = &hptep->v;
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while (1) {
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if (!test_and_set_bit(HPTE_LOCK_BIT, word))
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break;
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while(test_bit(HPTE_LOCK_BIT, word))
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cpu_relax();
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}
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}
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static inline void native_unlock_hpte(hpte_t *hptep)
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{
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unsigned long *word = &hptep->v;
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asm volatile("lwsync":::"memory");
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clear_bit(HPTE_LOCK_BIT, word);
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}
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long native_hpte_insert(unsigned long hpte_group, unsigned long va,
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unsigned long prpn, unsigned long vflags,
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unsigned long rflags)
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{
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hpte_t *hptep = htab_address + hpte_group;
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unsigned long hpte_v, hpte_r;
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int i;
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for (i = 0; i < HPTES_PER_GROUP; i++) {
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if (! (hptep->v & HPTE_V_VALID)) {
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/* retry with lock held */
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native_lock_hpte(hptep);
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if (! (hptep->v & HPTE_V_VALID))
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break;
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native_unlock_hpte(hptep);
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}
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hptep++;
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}
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if (i == HPTES_PER_GROUP)
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return -1;
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hpte_v = (va >> 23) << HPTE_V_AVPN_SHIFT | vflags | HPTE_V_VALID;
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if (vflags & HPTE_V_LARGE)
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va &= ~(1UL << HPTE_V_AVPN_SHIFT);
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hpte_r = (prpn << HPTE_R_RPN_SHIFT) | rflags;
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hptep->r = hpte_r;
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/* Guarantee the second dword is visible before the valid bit */
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__asm__ __volatile__ ("eieio" : : : "memory");
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/*
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* Now set the first dword including the valid bit
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* NOTE: this also unlocks the hpte
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*/
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hptep->v = hpte_v;
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__asm__ __volatile__ ("ptesync" : : : "memory");
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return i | (!!(vflags & HPTE_V_SECONDARY) << 3);
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}
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static long native_hpte_remove(unsigned long hpte_group)
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{
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hpte_t *hptep;
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int i;
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int slot_offset;
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unsigned long hpte_v;
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/* pick a random entry to start at */
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slot_offset = mftb() & 0x7;
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for (i = 0; i < HPTES_PER_GROUP; i++) {
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hptep = htab_address + hpte_group + slot_offset;
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hpte_v = hptep->v;
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if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) {
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/* retry with lock held */
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native_lock_hpte(hptep);
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hpte_v = hptep->v;
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if ((hpte_v & HPTE_V_VALID)
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&& !(hpte_v & HPTE_V_BOLTED))
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break;
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native_unlock_hpte(hptep);
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}
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slot_offset++;
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slot_offset &= 0x7;
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}
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if (i == HPTES_PER_GROUP)
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return -1;
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/* Invalidate the hpte. NOTE: this also unlocks it */
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hptep->v = 0;
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return i;
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}
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static inline void set_pp_bit(unsigned long pp, hpte_t *addr)
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{
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unsigned long old;
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unsigned long *p = &addr->r;
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__asm__ __volatile__(
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"1: ldarx %0,0,%3\n\
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rldimi %0,%2,0,61\n\
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stdcx. %0,0,%3\n\
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bne 1b"
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: "=&r" (old), "=m" (*p)
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: "r" (pp), "r" (p), "m" (*p)
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: "cc");
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}
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/*
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* Only works on small pages. Yes its ugly to have to check each slot in
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* the group but we only use this during bootup.
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*/
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static long native_hpte_find(unsigned long vpn)
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{
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hpte_t *hptep;
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unsigned long hash;
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unsigned long i, j;
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long slot;
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unsigned long hpte_v;
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hash = hpt_hash(vpn, 0);
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for (j = 0; j < 2; j++) {
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slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
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for (i = 0; i < HPTES_PER_GROUP; i++) {
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hptep = htab_address + slot;
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hpte_v = hptep->v;
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if ((HPTE_V_AVPN_VAL(hpte_v) == (vpn >> 11))
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&& (hpte_v & HPTE_V_VALID)
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&& ( !!(hpte_v & HPTE_V_SECONDARY) == j)) {
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/* HPTE matches */
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if (j)
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slot = -slot;
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return slot;
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}
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++slot;
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}
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hash = ~hash;
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}
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return -1;
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}
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static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
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unsigned long va, int large, int local)
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{
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hpte_t *hptep = htab_address + slot;
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unsigned long hpte_v;
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unsigned long avpn = va >> 23;
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int ret = 0;
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if (large)
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avpn &= ~1;
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native_lock_hpte(hptep);
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hpte_v = hptep->v;
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/* Even if we miss, we need to invalidate the TLB */
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if ((HPTE_V_AVPN_VAL(hpte_v) != avpn)
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|| !(hpte_v & HPTE_V_VALID)) {
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native_unlock_hpte(hptep);
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ret = -1;
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} else {
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set_pp_bit(newpp, hptep);
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native_unlock_hpte(hptep);
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}
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/* Ensure it is out of the tlb too */
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if (cpu_has_feature(CPU_FTR_TLBIEL) && !large && local) {
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tlbiel(va);
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} else {
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int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
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if (lock_tlbie)
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spin_lock(&native_tlbie_lock);
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tlbie(va, large);
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if (lock_tlbie)
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spin_unlock(&native_tlbie_lock);
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}
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return ret;
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}
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/*
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* Update the page protection bits. Intended to be used to create
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* guard pages for kernel data structures on pages which are bolted
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* in the HPT. Assumes pages being operated on will not be stolen.
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* Does not work on large pages.
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*
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* No need to lock here because we should be the only user.
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*/
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static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea)
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{
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unsigned long vsid, va, vpn, flags = 0;
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long slot;
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hpte_t *hptep;
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int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
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vsid = get_kernel_vsid(ea);
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va = (vsid << 28) | (ea & 0x0fffffff);
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vpn = va >> PAGE_SHIFT;
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slot = native_hpte_find(vpn);
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if (slot == -1)
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panic("could not find page to bolt\n");
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hptep = htab_address + slot;
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set_pp_bit(newpp, hptep);
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/* Ensure it is out of the tlb too */
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if (lock_tlbie)
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spin_lock_irqsave(&native_tlbie_lock, flags);
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tlbie(va, 0);
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if (lock_tlbie)
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spin_unlock_irqrestore(&native_tlbie_lock, flags);
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}
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static void native_hpte_invalidate(unsigned long slot, unsigned long va,
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int large, int local)
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{
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hpte_t *hptep = htab_address + slot;
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unsigned long hpte_v;
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unsigned long avpn = va >> 23;
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unsigned long flags;
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int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
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if (large)
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avpn &= ~1;
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local_irq_save(flags);
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native_lock_hpte(hptep);
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hpte_v = hptep->v;
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/* Even if we miss, we need to invalidate the TLB */
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if ((HPTE_V_AVPN_VAL(hpte_v) != avpn)
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|| !(hpte_v & HPTE_V_VALID)) {
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native_unlock_hpte(hptep);
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} else {
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/* Invalidate the hpte. NOTE: this also unlocks it */
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hptep->v = 0;
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}
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/* Invalidate the tlb */
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if (cpu_has_feature(CPU_FTR_TLBIEL) && !large && local) {
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tlbiel(va);
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} else {
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if (lock_tlbie)
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spin_lock(&native_tlbie_lock);
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tlbie(va, large);
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if (lock_tlbie)
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spin_unlock(&native_tlbie_lock);
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}
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local_irq_restore(flags);
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}
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/*
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* clear all mappings on kexec. All cpus are in real mode (or they will
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* be when they isi), and we are the only one left. We rely on our kernel
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* mapping being 0xC0's and the hardware ignoring those two real bits.
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*
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* TODO: add batching support when enabled. remember, no dynamic memory here,
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* athough there is the control page available...
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*/
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static void native_hpte_clear(void)
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{
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unsigned long slot, slots, flags;
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hpte_t *hptep = htab_address;
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unsigned long hpte_v;
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unsigned long pteg_count;
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pteg_count = htab_hash_mask + 1;
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local_irq_save(flags);
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/* we take the tlbie lock and hold it. Some hardware will
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* deadlock if we try to tlbie from two processors at once.
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*/
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spin_lock(&native_tlbie_lock);
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slots = pteg_count * HPTES_PER_GROUP;
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for (slot = 0; slot < slots; slot++, hptep++) {
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/*
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* we could lock the pte here, but we are the only cpu
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* running, right? and for crash dump, we probably
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* don't want to wait for a maybe bad cpu.
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*/
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hpte_v = hptep->v;
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if (hpte_v & HPTE_V_VALID) {
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hptep->v = 0;
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tlbie(slot2va(hpte_v, slot), hpte_v & HPTE_V_LARGE);
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}
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}
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spin_unlock(&native_tlbie_lock);
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local_irq_restore(flags);
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}
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static void native_flush_hash_range(unsigned long number, int local)
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{
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unsigned long va, vpn, hash, secondary, slot, flags, avpn;
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int i, j;
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hpte_t *hptep;
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unsigned long hpte_v;
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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/* XXX fix for large ptes */
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unsigned long large = 0;
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local_irq_save(flags);
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j = 0;
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for (i = 0; i < number; i++) {
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va = batch->vaddr[j];
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if (large)
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vpn = va >> HPAGE_SHIFT;
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else
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vpn = va >> PAGE_SHIFT;
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hash = hpt_hash(vpn, large);
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secondary = (pte_val(batch->pte[i]) & _PAGE_SECONDARY) >> 15;
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if (secondary)
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hash = ~hash;
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slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
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slot += (pte_val(batch->pte[i]) & _PAGE_GROUP_IX) >> 12;
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hptep = htab_address + slot;
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avpn = va >> 23;
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if (large)
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avpn &= ~0x1UL;
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native_lock_hpte(hptep);
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hpte_v = hptep->v;
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/* Even if we miss, we need to invalidate the TLB */
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if ((HPTE_V_AVPN_VAL(hpte_v) != avpn)
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|| !(hpte_v & HPTE_V_VALID)) {
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native_unlock_hpte(hptep);
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} else {
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/* Invalidate the hpte. NOTE: this also unlocks it */
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hptep->v = 0;
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}
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j++;
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}
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if (cpu_has_feature(CPU_FTR_TLBIEL) && !large && local) {
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asm volatile("ptesync":::"memory");
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for (i = 0; i < j; i++)
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__tlbiel(batch->vaddr[i]);
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asm volatile("ptesync":::"memory");
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} else {
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int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
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if (lock_tlbie)
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spin_lock(&native_tlbie_lock);
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asm volatile("ptesync":::"memory");
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for (i = 0; i < j; i++)
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__tlbie(batch->vaddr[i], 0);
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asm volatile("eieio; tlbsync; ptesync":::"memory");
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if (lock_tlbie)
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spin_unlock(&native_tlbie_lock);
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}
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local_irq_restore(flags);
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}
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#ifdef CONFIG_PPC_PSERIES
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/* Disable TLB batching on nighthawk */
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static inline int tlb_batching_enabled(void)
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{
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struct device_node *root = of_find_node_by_path("/");
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int enabled = 1;
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if (root) {
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const char *model = get_property(root, "model", NULL);
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if (model && !strcmp(model, "IBM,9076-N81"))
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enabled = 0;
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of_node_put(root);
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}
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return enabled;
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}
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#else
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static inline int tlb_batching_enabled(void)
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{
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return 1;
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}
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#endif
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void hpte_init_native(void)
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{
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ppc_md.hpte_invalidate = native_hpte_invalidate;
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ppc_md.hpte_updatepp = native_hpte_updatepp;
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ppc_md.hpte_updateboltedpp = native_hpte_updateboltedpp;
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ppc_md.hpte_insert = native_hpte_insert;
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ppc_md.hpte_remove = native_hpte_remove;
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ppc_md.hpte_clear_all = native_hpte_clear;
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if (tlb_batching_enabled())
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ppc_md.flush_hash_range = native_flush_hash_range;
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htab_finish_init();
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}
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