24d4076734
arch_initcall() runs after the machine init function which means that any configuration of GPIO pins must currently be done later on, for example in callbacks from drivers. Move the initialisation earlier in order to allow machines to configure GPIOs directly in their init functions rather than having to have a callback invoked later on. Some other ARM platforms use this method. Other solutions for this include providing a special interface for setting up GPIOs en masse, adding callbacks to do the GPIO configuration from devices and doing the GPIO configuration implicitly. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
421 lines
9.9 KiB
C
421 lines
9.9 KiB
C
/* arch/arm/plat-s3c64xx/gpiolib.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - GPIOlib support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <mach/gpio.h>
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#include <mach/gpio-core.h>
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#include <plat/gpio-cfg.h>
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#include <plat/gpio-cfg-helpers.h>
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#include <plat/regs-gpio.h>
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/* GPIO bank summary:
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*
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* Bank GPIOs Style SlpCon ExtInt Group
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* A 8 4Bit Yes 1
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* B 7 4Bit Yes 1
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* C 8 4Bit Yes 2
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* D 5 4Bit Yes 3
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* E 5 4Bit Yes None
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* F 16 2Bit Yes 4 [1]
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* G 7 4Bit Yes 5
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* H 10 4Bit[2] Yes 6
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* I 16 2Bit Yes None
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* J 12 2Bit Yes None
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* K 16 4Bit[2] No None
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* L 15 4Bit[2] No None
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* M 6 4Bit No IRQ_EINT
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* N 16 2Bit No IRQ_EINT
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* O 16 2Bit Yes 7
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* P 15 2Bit Yes 8
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* Q 9 2Bit Yes 9
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*
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* [1] BANKF pins 14,15 do not form part of the external interrupt sources
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* [2] BANK has two control registers, GPxCON0 and GPxCON1
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*/
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#define OFF_GPCON (0x00)
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#define OFF_GPDAT (0x04)
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#define con_4bit_shift(__off) ((__off) * 4)
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#if 1
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#define gpio_dbg(x...) do { } while(0)
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#else
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#define gpio_dbg(x...) printk(KERN_DEBUG ## x)
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#endif
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/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where
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* the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
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* following example:
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*
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* base + 0x00: Control register, 4 bits per gpio
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x04: Data register, 1 bit per gpio
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* bit n: data bit n
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*
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* Note, since the data register is one bit per gpio and is at base + 0x4
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* we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
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* the output.
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*/
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static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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unsigned long con;
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con = __raw_readl(base + OFF_GPCON);
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con &= ~(0xf << con_4bit_shift(offset));
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__raw_writel(con, base + OFF_GPCON);
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gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
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return 0;
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}
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static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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unsigned long con;
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unsigned long dat;
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con = __raw_readl(base + OFF_GPCON);
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con &= ~(0xf << con_4bit_shift(offset));
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con |= 0x1 << con_4bit_shift(offset);
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dat = __raw_readl(base + OFF_GPDAT);
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if (value)
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dat |= 1 << offset;
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else
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dat &= ~(1 << offset);
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__raw_writel(dat, base + OFF_GPDAT);
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__raw_writel(con, base + OFF_GPCON);
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__raw_writel(dat, base + OFF_GPDAT);
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gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
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return 0;
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}
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/* The next set of routines are for the case where the GPIO configuration
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* registers are 4 bits per GPIO but there is more than one register (the
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* bank has more than 8 GPIOs.
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*
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* This case is the similar to the 4 bit case, but the registers are as
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* follows:
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*
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* base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
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* gpio n: 4 bits starting at (4*n)
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* 0000 = input, 0001 = output, others mean special-function
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* base + 0x08: Data register, 1 bit per gpio
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* bit n: data bit n
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*
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* To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
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* store the 'base + 0x4' address so that these routines see the data
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* register at ourchip->base + 0x04.
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*/
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static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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void __iomem *regcon = base;
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unsigned long con;
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if (offset > 7)
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offset -= 8;
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else
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regcon -= 4;
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con = __raw_readl(regcon);
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con &= ~(0xf << con_4bit_shift(offset));
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__raw_writel(con, regcon);
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gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
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return 0;
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}
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static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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void __iomem *regcon = base;
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unsigned long con;
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unsigned long dat;
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if (offset > 7)
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offset -= 8;
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else
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regcon -= 4;
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con = __raw_readl(regcon);
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con &= ~(0xf << con_4bit_shift(offset));
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con |= 0x1 << con_4bit_shift(offset);
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dat = __raw_readl(base + OFF_GPDAT);
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if (value)
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dat |= 1 << offset;
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else
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dat &= ~(1 << offset);
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__raw_writel(dat, base + OFF_GPDAT);
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__raw_writel(con, regcon);
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__raw_writel(dat, base + OFF_GPDAT);
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gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
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return 0;
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}
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static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
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.cfg_eint = 7,
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
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.cfg_eint = 3,
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_chip gpio_4bit[] = {
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{
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.base = S3C64XX_GPA_BASE,
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.config = &gpio_4bit_cfg_eint0111,
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.chip = {
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.base = S3C64XX_GPA(0),
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.ngpio = S3C64XX_GPIO_A_NR,
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.label = "GPA",
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},
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}, {
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.base = S3C64XX_GPB_BASE,
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.config = &gpio_4bit_cfg_eint0111,
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.chip = {
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.base = S3C64XX_GPB(0),
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.ngpio = S3C64XX_GPIO_B_NR,
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.label = "GPB",
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},
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}, {
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.base = S3C64XX_GPC_BASE,
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.config = &gpio_4bit_cfg_eint0111,
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.chip = {
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.base = S3C64XX_GPC(0),
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.ngpio = S3C64XX_GPIO_C_NR,
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.label = "GPC",
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},
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}, {
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.base = S3C64XX_GPD_BASE,
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.config = &gpio_4bit_cfg_eint0111,
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.chip = {
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.base = S3C64XX_GPD(0),
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.ngpio = S3C64XX_GPIO_D_NR,
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.label = "GPD",
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},
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}, {
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.base = S3C64XX_GPE_BASE,
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.config = &gpio_4bit_cfg_noint,
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.chip = {
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.base = S3C64XX_GPE(0),
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.ngpio = S3C64XX_GPIO_E_NR,
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.label = "GPE",
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},
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}, {
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.base = S3C64XX_GPG_BASE,
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.config = &gpio_4bit_cfg_eint0111,
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.chip = {
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.base = S3C64XX_GPG(0),
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.ngpio = S3C64XX_GPIO_G_NR,
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.label = "GPG",
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},
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}, {
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.base = S3C64XX_GPM_BASE,
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.config = &gpio_4bit_cfg_eint0011,
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.chip = {
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.base = S3C64XX_GPM(0),
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.ngpio = S3C64XX_GPIO_M_NR,
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.label = "GPM",
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},
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},
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};
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static struct s3c_gpio_chip gpio_4bit2[] = {
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{
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.base = S3C64XX_GPH_BASE + 0x4,
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.config = &gpio_4bit_cfg_eint0111,
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.chip = {
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.base = S3C64XX_GPH(0),
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.ngpio = S3C64XX_GPIO_H_NR,
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.label = "GPH",
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},
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}, {
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.base = S3C64XX_GPK_BASE + 0x4,
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.config = &gpio_4bit_cfg_noint,
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.chip = {
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.base = S3C64XX_GPK(0),
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.ngpio = S3C64XX_GPIO_K_NR,
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.label = "GPK",
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},
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}, {
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.base = S3C64XX_GPL_BASE + 0x4,
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.config = &gpio_4bit_cfg_eint0011,
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.chip = {
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.base = S3C64XX_GPL(0),
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.ngpio = S3C64XX_GPIO_L_NR,
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.label = "GPL",
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},
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},
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};
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static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
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.set_config = s3c_gpio_setcfg_s3c24xx,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
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.cfg_eint = 2,
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.set_config = s3c_gpio_setcfg_s3c24xx,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
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.cfg_eint = 3,
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.set_config = s3c_gpio_setcfg_s3c24xx,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_chip gpio_2bit[] = {
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{
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.base = S3C64XX_GPF_BASE,
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.config = &gpio_2bit_cfg_eint11,
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.chip = {
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.base = S3C64XX_GPF(0),
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.ngpio = S3C64XX_GPIO_F_NR,
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.label = "GPF",
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},
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}, {
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.base = S3C64XX_GPI_BASE,
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.config = &gpio_2bit_cfg_noint,
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.chip = {
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.base = S3C64XX_GPI(0),
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.ngpio = S3C64XX_GPIO_I_NR,
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.label = "GPI",
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},
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}, {
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.base = S3C64XX_GPJ_BASE,
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.config = &gpio_2bit_cfg_noint,
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.chip = {
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.base = S3C64XX_GPJ(0),
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.ngpio = S3C64XX_GPIO_J_NR,
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.label = "GPJ",
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},
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}, {
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.base = S3C64XX_GPN_BASE,
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.config = &gpio_2bit_cfg_eint10,
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.chip = {
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.base = S3C64XX_GPN(0),
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.ngpio = S3C64XX_GPIO_N_NR,
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.label = "GPN",
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},
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}, {
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.base = S3C64XX_GPO_BASE,
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.config = &gpio_2bit_cfg_eint11,
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.chip = {
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.base = S3C64XX_GPO(0),
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.ngpio = S3C64XX_GPIO_O_NR,
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.label = "GPO",
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},
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}, {
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.base = S3C64XX_GPP_BASE,
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.config = &gpio_2bit_cfg_eint11,
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.chip = {
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.base = S3C64XX_GPP(0),
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.ngpio = S3C64XX_GPIO_P_NR,
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.label = "GPP",
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},
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}, {
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.base = S3C64XX_GPQ_BASE,
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.config = &gpio_2bit_cfg_eint11,
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.chip = {
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.base = S3C64XX_GPQ(0),
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.ngpio = S3C64XX_GPIO_Q_NR,
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.label = "GPQ",
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},
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},
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};
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static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
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{
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chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
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chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
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}
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static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
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{
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chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
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chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
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}
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static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
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int nr_chips,
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void (*fn)(struct s3c_gpio_chip *))
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{
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for (; nr_chips > 0; nr_chips--, chips++) {
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if (fn)
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(fn)(chips);
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s3c_gpiolib_add(chips);
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}
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}
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static __init int s3c64xx_gpiolib_init(void)
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{
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s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
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s3c64xx_gpiolib_add_4bit);
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s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
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s3c64xx_gpiolib_add_4bit2);
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s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL);
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return 0;
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}
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core_initcall(s3c64xx_gpiolib_init);
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