ff3fcac949
The musb/cppi41 glue layer is capable of handling transactions that span over more than one USB packet by reloading the DMA descriptors partially. An urb is considered completed when either its transfer buffer has been filled entirely (actual_length == transfer_buffer_length) or if a packet in the stream has less bytes than the endpoint's wMaxPacketSize. Once one of the above conditions is met, musb_dma_completion() is called from cppi41_trans_done(). However, the final decision whether or not to return the urb to its owner is made by the core and its determination of the variable 'done' in musb_host_rx(). This code has currently no way of knowing what the size of the last packet was, and whether or not to give back the urb due to a short read. Fix this by introducing a new boolean flag in 'struct dma_channel', and set it from musb_cppi41.c. If set, it will make the core do what the DMA layer decided and complete the urb. Signed-off-by: Daniel Mack <zonque@gmail.com> Acked-by: George Cherian <george.cherian@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
196 lines
6.3 KiB
C
196 lines
6.3 KiB
C
/*
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* MUSB OTG driver DMA controller abstraction
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*
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* Copyright 2005 Mentor Graphics Corporation
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* Copyright (C) 2005-2006 by Texas Instruments
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* Copyright (C) 2006-2007 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __MUSB_DMA_H__
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#define __MUSB_DMA_H__
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struct musb_hw_ep;
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/*
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* DMA Controller Abstraction
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*
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* DMA Controllers are abstracted to allow use of a variety of different
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* implementations of DMA, as allowed by the Inventra USB cores. On the
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* host side, usbcore sets up the DMA mappings and flushes caches; on the
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* peripheral side, the gadget controller driver does. Responsibilities
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* of a DMA controller driver include:
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*
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* - Handling the details of moving multiple USB packets
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* in cooperation with the Inventra USB core, including especially
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* the correct RX side treatment of short packets and buffer-full
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* states (both of which terminate transfers).
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*
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* - Knowing the correlation between dma channels and the
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* Inventra core's local endpoint resources and data direction.
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*
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* - Maintaining a list of allocated/available channels.
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*
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* - Updating channel status on interrupts,
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* whether shared with the Inventra core or separate.
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*/
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#define DMA_ADDR_INVALID (~(dma_addr_t)0)
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#ifdef CONFIG_MUSB_PIO_ONLY
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#define is_dma_capable() (0)
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#else
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#define is_dma_capable() (1)
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#endif
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#if defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TI_CPPI41_DMA)
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#define is_cppi_enabled() 1
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#else
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#define is_cppi_enabled() 0
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#endif
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#ifdef CONFIG_USB_TUSB_OMAP_DMA
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#define tusb_dma_omap() 1
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#else
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#define tusb_dma_omap() 0
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#endif
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/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
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* Only allow DMA mode 1 to be used when the USB will actually generate the
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* interrupts we expect.
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*/
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#ifdef CONFIG_BLACKFIN
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# undef USE_MODE1
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# if !ANOMALY_05000456
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# define USE_MODE1
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# endif
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#endif
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/*
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* DMA channel status ... updated by the dma controller driver whenever that
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* status changes, and protected by the overall controller spinlock.
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*/
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enum dma_channel_status {
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/* unallocated */
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MUSB_DMA_STATUS_UNKNOWN,
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/* allocated ... but not busy, no errors */
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MUSB_DMA_STATUS_FREE,
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/* busy ... transactions are active */
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MUSB_DMA_STATUS_BUSY,
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/* transaction(s) aborted due to ... dma or memory bus error */
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MUSB_DMA_STATUS_BUS_ABORT,
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/* transaction(s) aborted due to ... core error or USB fault */
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MUSB_DMA_STATUS_CORE_ABORT
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};
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struct dma_controller;
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/**
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* struct dma_channel - A DMA channel.
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* @private_data: channel-private data
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* @max_len: the maximum number of bytes the channel can move in one
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* transaction (typically representing many USB maximum-sized packets)
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* @actual_len: how many bytes have been transferred
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* @status: current channel status (updated e.g. on interrupt)
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* @desired_mode: true if mode 1 is desired; false if mode 0 is desired
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*
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* channels are associated with an endpoint for the duration of at least
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* one usb transfer.
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*/
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struct dma_channel {
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void *private_data;
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/* FIXME not void* private_data, but a dma_controller * */
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size_t max_len;
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size_t actual_len;
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enum dma_channel_status status;
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bool desired_mode;
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bool rx_packet_done;
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};
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/*
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* dma_channel_status - return status of dma channel
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* @c: the channel
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*
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* Returns the software's view of the channel status. If that status is BUSY
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* then it's possible that the hardware has completed (or aborted) a transfer,
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* so the driver needs to update that status.
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*/
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static inline enum dma_channel_status
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dma_channel_status(struct dma_channel *c)
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{
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return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
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}
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/**
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* struct dma_controller - A DMA Controller.
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* @start: call this to start a DMA controller;
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* return 0 on success, else negative errno
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* @stop: call this to stop a DMA controller
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* return 0 on success, else negative errno
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* @channel_alloc: call this to allocate a DMA channel
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* @channel_release: call this to release a DMA channel
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* @channel_abort: call this to abort a pending DMA transaction,
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* returning it to FREE (but allocated) state
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*
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* Controllers manage dma channels.
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*/
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struct dma_controller {
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struct dma_channel *(*channel_alloc)(struct dma_controller *,
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struct musb_hw_ep *, u8 is_tx);
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void (*channel_release)(struct dma_channel *);
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int (*channel_program)(struct dma_channel *channel,
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u16 maxpacket, u8 mode,
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dma_addr_t dma_addr,
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u32 length);
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int (*channel_abort)(struct dma_channel *);
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int (*is_compatible)(struct dma_channel *channel,
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u16 maxpacket,
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void *buf, u32 length);
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};
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/* called after channel_program(), may indicate a fault */
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extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
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#ifdef CONFIG_MUSB_PIO_ONLY
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static inline struct dma_controller *dma_controller_create(struct musb *m,
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void __iomem *io)
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{
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return NULL;
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}
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static inline void dma_controller_destroy(struct dma_controller *d) { }
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#else
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extern struct dma_controller *dma_controller_create(struct musb *, void __iomem *);
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extern void dma_controller_destroy(struct dma_controller *);
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#endif
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#endif /* __MUSB_DMA_H__ */
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