57e65ad77f
The majority of configuration done in d40_phy_config() pertains to physical channels. Move the call over to runtime config which has different code paths for physical and logical channels already, and make it an exclusive physical channel config function as the name implies, and drop the is_log argument. Since we moved the call to runtime_config() it only gets called for device transfers, so encode the small snippet of configuration pertaining to memcpy channels into the d40_config_memcpy() function. Acked-by: Vinod Koul <vinod.koul@intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Lee Jones <lee.jones@linaro.org> [rewrote the commit message] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
471 lines
13 KiB
C
471 lines
13 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2007-2010
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* Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson SA
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson SA
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef STE_DMA40_LL_H
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#define STE_DMA40_LL_H
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#define D40_DREG_PCBASE 0x400
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#define D40_DREG_PCDELTA (8 * 4)
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#define D40_LLI_ALIGN 16 /* LLI alignment must be 16 bytes. */
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#define D40_LCPA_CHAN_SIZE 32
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#define D40_LCPA_CHAN_DST_DELTA 16
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#define D40_TYPE_TO_GROUP(type) (type / 16)
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#define D40_TYPE_TO_EVENT(type) (type % 16)
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#define D40_GROUP_SIZE 8
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#define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)
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/* Most bits of the CFG register are the same in log as in phy mode */
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#define D40_SREG_CFG_MST_POS 15
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#define D40_SREG_CFG_TIM_POS 14
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#define D40_SREG_CFG_EIM_POS 13
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#define D40_SREG_CFG_LOG_INCR_POS 12
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#define D40_SREG_CFG_PHY_PEN_POS 12
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#define D40_SREG_CFG_PSIZE_POS 10
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#define D40_SREG_CFG_ESIZE_POS 8
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#define D40_SREG_CFG_PRI_POS 7
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#define D40_SREG_CFG_LBE_POS 6
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#define D40_SREG_CFG_LOG_GIM_POS 5
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#define D40_SREG_CFG_LOG_MFU_POS 4
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#define D40_SREG_CFG_PHY_TM_POS 4
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#define D40_SREG_CFG_PHY_EVTL_POS 0
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/* Standard channel parameters - basic mode (element register) */
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#define D40_SREG_ELEM_PHY_ECNT_POS 16
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#define D40_SREG_ELEM_PHY_EIDX_POS 0
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#define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
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/* Standard channel parameters - basic mode (Link register) */
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#define D40_SREG_LNK_PHY_TCP_POS 0
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#define D40_SREG_LNK_PHY_LMP_POS 1
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#define D40_SREG_LNK_PHY_PRE_POS 2
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/*
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* Source destination link address. Contains the
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* 29-bit byte word aligned address of the reload area.
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*/
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#define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL
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/* Standard basic channel logical mode */
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/* Element register */
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#define D40_SREG_ELEM_LOG_ECNT_POS 16
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#define D40_SREG_ELEM_LOG_LIDX_POS 8
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#define D40_SREG_ELEM_LOG_LOS_POS 1
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#define D40_SREG_ELEM_LOG_TCP_POS 0
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#define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
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/* Link register */
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#define D40_EVENTLINE_POS(i) (2 * i)
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#define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
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/* Standard basic channel logical params in memory */
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/* LCSP0 */
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#define D40_MEM_LCSP0_ECNT_POS 16
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#define D40_MEM_LCSP0_SPTR_POS 0
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#define D40_MEM_LCSP0_ECNT_MASK (0xFFFF << D40_MEM_LCSP0_ECNT_POS)
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#define D40_MEM_LCSP0_SPTR_MASK (0xFFFF << D40_MEM_LCSP0_SPTR_POS)
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/* LCSP1 */
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#define D40_MEM_LCSP1_SPTR_POS 16
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#define D40_MEM_LCSP1_SCFG_MST_POS 15
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#define D40_MEM_LCSP1_SCFG_TIM_POS 14
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#define D40_MEM_LCSP1_SCFG_EIM_POS 13
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#define D40_MEM_LCSP1_SCFG_INCR_POS 12
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#define D40_MEM_LCSP1_SCFG_PSIZE_POS 10
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#define D40_MEM_LCSP1_SCFG_ESIZE_POS 8
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#define D40_MEM_LCSP1_SLOS_POS 1
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#define D40_MEM_LCSP1_STCP_POS 0
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#define D40_MEM_LCSP1_SPTR_MASK (0xFFFF << D40_MEM_LCSP1_SPTR_POS)
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#define D40_MEM_LCSP1_SCFG_TIM_MASK (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
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#define D40_MEM_LCSP1_SCFG_INCR_MASK (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
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#define D40_MEM_LCSP1_SCFG_PSIZE_MASK (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
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#define D40_MEM_LCSP1_SLOS_MASK (0x7F << D40_MEM_LCSP1_SLOS_POS)
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#define D40_MEM_LCSP1_STCP_MASK (0x1 << D40_MEM_LCSP1_STCP_POS)
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/* LCSP2 */
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#define D40_MEM_LCSP2_ECNT_POS 16
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#define D40_MEM_LCSP2_ECNT_MASK (0xFFFF << D40_MEM_LCSP2_ECNT_POS)
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/* LCSP3 */
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#define D40_MEM_LCSP3_DCFG_MST_POS 15
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#define D40_MEM_LCSP3_DCFG_TIM_POS 14
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#define D40_MEM_LCSP3_DCFG_EIM_POS 13
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#define D40_MEM_LCSP3_DCFG_INCR_POS 12
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#define D40_MEM_LCSP3_DCFG_PSIZE_POS 10
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#define D40_MEM_LCSP3_DCFG_ESIZE_POS 8
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#define D40_MEM_LCSP3_DLOS_POS 1
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#define D40_MEM_LCSP3_DTCP_POS 0
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#define D40_MEM_LCSP3_DLOS_MASK (0x7F << D40_MEM_LCSP3_DLOS_POS)
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#define D40_MEM_LCSP3_DTCP_MASK (0x1 << D40_MEM_LCSP3_DTCP_POS)
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/* Standard channel parameter register offsets */
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#define D40_CHAN_REG_SSCFG 0x00
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#define D40_CHAN_REG_SSELT 0x04
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#define D40_CHAN_REG_SSPTR 0x08
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#define D40_CHAN_REG_SSLNK 0x0C
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#define D40_CHAN_REG_SDCFG 0x10
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#define D40_CHAN_REG_SDELT 0x14
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#define D40_CHAN_REG_SDPTR 0x18
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#define D40_CHAN_REG_SDLNK 0x1C
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/* DMA Register Offsets */
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#define D40_DREG_GCC 0x000
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#define D40_DREG_GCC_ENA 0x1
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/* This assumes that there are only 4 event groups */
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#define D40_DREG_GCC_ENABLE_ALL 0x3ff01
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#define D40_DREG_GCC_EVTGRP_POS 8
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#define D40_DREG_GCC_SRC 0
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#define D40_DREG_GCC_DST 1
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#define D40_DREG_GCC_EVTGRP_ENA(x, y) \
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(1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y))
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#define D40_DREG_PRTYP 0x004
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#define D40_DREG_PRSME 0x008
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#define D40_DREG_PRSMO 0x00C
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#define D40_DREG_PRMSE 0x010
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#define D40_DREG_PRMSO 0x014
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#define D40_DREG_PRMOE 0x018
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#define D40_DREG_PRMOO 0x01C
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#define D40_DREG_PRMO_PCHAN_BASIC 0x1
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#define D40_DREG_PRMO_PCHAN_MODULO 0x2
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#define D40_DREG_PRMO_PCHAN_DOUBLE_DST 0x3
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#define D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG 0x1
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#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY 0x2
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#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG 0x3
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#define D40_DREG_LCPA 0x020
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#define D40_DREG_LCLA 0x024
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#define D40_DREG_SSEG1 0x030
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#define D40_DREG_SSEG2 0x034
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#define D40_DREG_SSEG3 0x038
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#define D40_DREG_SSEG4 0x03C
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#define D40_DREG_SCEG1 0x040
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#define D40_DREG_SCEG2 0x044
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#define D40_DREG_SCEG3 0x048
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#define D40_DREG_SCEG4 0x04C
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#define D40_DREG_ACTIVE 0x050
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#define D40_DREG_ACTIVO 0x054
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#define D40_DREG_CIDMOD 0x058
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#define D40_DREG_TCIDV 0x05C
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#define D40_DREG_PCMIS 0x060
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#define D40_DREG_PCICR 0x064
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#define D40_DREG_PCTIS 0x068
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#define D40_DREG_PCEIS 0x06C
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#define D40_DREG_SPCMIS 0x070
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#define D40_DREG_SPCICR 0x074
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#define D40_DREG_SPCTIS 0x078
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#define D40_DREG_SPCEIS 0x07C
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#define D40_DREG_LCMIS0 0x080
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#define D40_DREG_LCMIS1 0x084
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#define D40_DREG_LCMIS2 0x088
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#define D40_DREG_LCMIS3 0x08C
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#define D40_DREG_LCICR0 0x090
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#define D40_DREG_LCICR1 0x094
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#define D40_DREG_LCICR2 0x098
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#define D40_DREG_LCICR3 0x09C
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#define D40_DREG_LCTIS0 0x0A0
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#define D40_DREG_LCTIS1 0x0A4
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#define D40_DREG_LCTIS2 0x0A8
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#define D40_DREG_LCTIS3 0x0AC
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#define D40_DREG_LCEIS0 0x0B0
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#define D40_DREG_LCEIS1 0x0B4
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#define D40_DREG_LCEIS2 0x0B8
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#define D40_DREG_LCEIS3 0x0BC
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#define D40_DREG_SLCMIS1 0x0C0
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#define D40_DREG_SLCMIS2 0x0C4
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#define D40_DREG_SLCMIS3 0x0C8
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#define D40_DREG_SLCMIS4 0x0CC
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#define D40_DREG_SLCICR1 0x0D0
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#define D40_DREG_SLCICR2 0x0D4
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#define D40_DREG_SLCICR3 0x0D8
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#define D40_DREG_SLCICR4 0x0DC
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#define D40_DREG_SLCTIS1 0x0E0
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#define D40_DREG_SLCTIS2 0x0E4
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#define D40_DREG_SLCTIS3 0x0E8
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#define D40_DREG_SLCTIS4 0x0EC
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#define D40_DREG_SLCEIS1 0x0F0
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#define D40_DREG_SLCEIS2 0x0F4
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#define D40_DREG_SLCEIS3 0x0F8
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#define D40_DREG_SLCEIS4 0x0FC
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#define D40_DREG_FSESS1 0x100
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#define D40_DREG_FSESS2 0x104
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#define D40_DREG_FSEBS1 0x108
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#define D40_DREG_FSEBS2 0x10C
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#define D40_DREG_PSEG1 0x110
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#define D40_DREG_PSEG2 0x114
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#define D40_DREG_PSEG3 0x118
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#define D40_DREG_PSEG4 0x11C
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#define D40_DREG_PCEG1 0x120
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#define D40_DREG_PCEG2 0x124
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#define D40_DREG_PCEG3 0x128
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#define D40_DREG_PCEG4 0x12C
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#define D40_DREG_RSEG1 0x130
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#define D40_DREG_RSEG2 0x134
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#define D40_DREG_RSEG3 0x138
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#define D40_DREG_RSEG4 0x13C
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#define D40_DREG_RCEG1 0x140
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#define D40_DREG_RCEG2 0x144
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#define D40_DREG_RCEG3 0x148
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#define D40_DREG_RCEG4 0x14C
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#define D40_DREG_PREFOT 0x15C
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#define D40_DREG_EXTCFG 0x160
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#define D40_DREG_CPSEG1 0x200
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#define D40_DREG_CPSEG2 0x204
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#define D40_DREG_CPSEG3 0x208
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#define D40_DREG_CPSEG4 0x20C
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#define D40_DREG_CPSEG5 0x210
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#define D40_DREG_CPCEG1 0x220
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#define D40_DREG_CPCEG2 0x224
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#define D40_DREG_CPCEG3 0x228
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#define D40_DREG_CPCEG4 0x22C
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#define D40_DREG_CPCEG5 0x230
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#define D40_DREG_CRSEG1 0x240
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#define D40_DREG_CRSEG2 0x244
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#define D40_DREG_CRSEG3 0x248
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#define D40_DREG_CRSEG4 0x24C
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#define D40_DREG_CRSEG5 0x250
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#define D40_DREG_CRCEG1 0x260
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#define D40_DREG_CRCEG2 0x264
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#define D40_DREG_CRCEG3 0x268
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#define D40_DREG_CRCEG4 0x26C
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#define D40_DREG_CRCEG5 0x270
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#define D40_DREG_CFSESS1 0x280
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#define D40_DREG_CFSESS2 0x284
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#define D40_DREG_CFSESS3 0x288
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#define D40_DREG_CFSEBS1 0x290
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#define D40_DREG_CFSEBS2 0x294
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#define D40_DREG_CFSEBS3 0x298
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#define D40_DREG_CLCMIS1 0x300
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#define D40_DREG_CLCMIS2 0x304
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#define D40_DREG_CLCMIS3 0x308
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#define D40_DREG_CLCMIS4 0x30C
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#define D40_DREG_CLCMIS5 0x310
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#define D40_DREG_CLCICR1 0x320
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#define D40_DREG_CLCICR2 0x324
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#define D40_DREG_CLCICR3 0x328
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#define D40_DREG_CLCICR4 0x32C
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#define D40_DREG_CLCICR5 0x330
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#define D40_DREG_CLCTIS1 0x340
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#define D40_DREG_CLCTIS2 0x344
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#define D40_DREG_CLCTIS3 0x348
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#define D40_DREG_CLCTIS4 0x34C
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#define D40_DREG_CLCTIS5 0x350
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#define D40_DREG_CLCEIS1 0x360
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#define D40_DREG_CLCEIS2 0x364
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#define D40_DREG_CLCEIS3 0x368
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#define D40_DREG_CLCEIS4 0x36C
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#define D40_DREG_CLCEIS5 0x370
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#define D40_DREG_CPCMIS 0x380
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#define D40_DREG_CPCICR 0x384
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#define D40_DREG_CPCTIS 0x388
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#define D40_DREG_CPCEIS 0x38C
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#define D40_DREG_SCCIDA1 0xE80
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#define D40_DREG_SCCIDA2 0xE90
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#define D40_DREG_SCCIDA3 0xEA0
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#define D40_DREG_SCCIDA4 0xEB0
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#define D40_DREG_SCCIDA5 0xEC0
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#define D40_DREG_SCCIDB1 0xE84
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#define D40_DREG_SCCIDB2 0xE94
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#define D40_DREG_SCCIDB3 0xEA4
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#define D40_DREG_SCCIDB4 0xEB4
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#define D40_DREG_SCCIDB5 0xEC4
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#define D40_DREG_PRSCCIDA 0xF80
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#define D40_DREG_PRSCCIDB 0xF84
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#define D40_DREG_STFU 0xFC8
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#define D40_DREG_ICFG 0xFCC
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#define D40_DREG_PERIPHID0 0xFE0
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#define D40_DREG_PERIPHID1 0xFE4
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#define D40_DREG_PERIPHID2 0xFE8
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#define D40_DREG_PERIPHID3 0xFEC
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#define D40_DREG_CELLID0 0xFF0
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#define D40_DREG_CELLID1 0xFF4
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#define D40_DREG_CELLID2 0xFF8
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#define D40_DREG_CELLID3 0xFFC
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/* LLI related structures */
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/**
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* struct d40_phy_lli - The basic configuration register for each physical
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* channel.
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*
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* @reg_cfg: The configuration register.
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* @reg_elt: The element register.
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* @reg_ptr: The pointer register.
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* @reg_lnk: The link register.
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*
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* These registers are set up for both physical and logical transfers
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* Note that the bit in each register means differently in logical and
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* physical(standard) mode.
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*
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* This struct must be 16 bytes aligned, and only contain physical registers
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* since it will be directly accessed by the DMA.
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*/
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struct d40_phy_lli {
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u32 reg_cfg;
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u32 reg_elt;
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u32 reg_ptr;
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u32 reg_lnk;
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};
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/**
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* struct d40_phy_lli_bidir - struct for a transfer.
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*
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* @src: Register settings for src channel.
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* @dst: Register settings for dst channel.
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*
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* All DMA transfers have a source and a destination.
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*/
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struct d40_phy_lli_bidir {
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struct d40_phy_lli *src;
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struct d40_phy_lli *dst;
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};
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/**
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* struct d40_log_lli - logical lli configuration
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*
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* @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.
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* @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.
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*
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* This struct must be 8 bytes aligned since it will be accessed directy by
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* the DMA. Never add any none hw mapped registers to this struct.
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*/
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struct d40_log_lli {
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u32 lcsp02;
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u32 lcsp13;
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};
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/**
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* struct d40_log_lli_bidir - For both src and dst
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*
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* @src: pointer to src lli configuration.
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* @dst: pointer to dst lli configuration.
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*
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* You always have a src and a dst when doing DMA transfers.
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*/
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struct d40_log_lli_bidir {
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struct d40_log_lli *src;
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struct d40_log_lli *dst;
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};
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/**
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* struct d40_log_lli_full - LCPA layout
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*
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* @lcsp0: Logical Channel Standard Param 0 - Src.
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* @lcsp1: Logical Channel Standard Param 1 - Src.
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* @lcsp2: Logical Channel Standard Param 2 - Dst.
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* @lcsp3: Logical Channel Standard Param 3 - Dst.
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*
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* This struct maps to LCPA physical memory layout. Must map to
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* the hw.
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*/
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struct d40_log_lli_full {
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u32 lcsp0;
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u32 lcsp1;
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u32 lcsp2;
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u32 lcsp3;
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};
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|
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/**
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* struct d40_def_lcsp - Default LCSP1 and LCSP3 settings
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*
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* @lcsp3: The default configuration for dst.
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* @lcsp1: The default configuration for src.
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|
*/
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struct d40_def_lcsp {
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u32 lcsp3;
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|
u32 lcsp1;
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};
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|
|
|
/* Physical channels */
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|
|
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enum d40_lli_flags {
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LLI_ADDR_INC = 1 << 0,
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LLI_TERM_INT = 1 << 1,
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|
LLI_CYCLIC = 1 << 2,
|
|
LLI_LAST_LINK = 1 << 3,
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|
};
|
|
|
|
void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
|
|
u32 *src_cfg,
|
|
u32 *dst_cfg);
|
|
|
|
void d40_log_cfg(struct stedma40_chan_cfg *cfg,
|
|
u32 *lcsp1,
|
|
u32 *lcsp2);
|
|
|
|
int d40_phy_sg_to_lli(struct scatterlist *sg,
|
|
int sg_len,
|
|
dma_addr_t target,
|
|
struct d40_phy_lli *lli,
|
|
dma_addr_t lli_phys,
|
|
u32 reg_cfg,
|
|
struct stedma40_half_channel_info *info,
|
|
struct stedma40_half_channel_info *otherinfo,
|
|
unsigned long flags);
|
|
|
|
/* Logical channels */
|
|
|
|
int d40_log_sg_to_lli(struct scatterlist *sg,
|
|
int sg_len,
|
|
dma_addr_t dev_addr,
|
|
struct d40_log_lli *lli_sg,
|
|
u32 lcsp13, /* src or dst*/
|
|
u32 data_width1, u32 data_width2);
|
|
|
|
void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
|
|
struct d40_log_lli *lli_dst,
|
|
struct d40_log_lli *lli_src,
|
|
int next, unsigned int flags);
|
|
|
|
void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
|
|
struct d40_log_lli *lli_dst,
|
|
struct d40_log_lli *lli_src,
|
|
int next, unsigned int flags);
|
|
|
|
#endif /* STE_DMA40_LLI_H */
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