0691bb1b5a
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main PLL go through a pre-divider before coming into the system. These registers were hidden for the CycloneV platform, but are now used for the ArriaV platform. This patch updates the clock driver to read the div-reg property for the socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
62 lines
1.6 KiB
C
62 lines
1.6 KiB
C
/*
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* Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
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*
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* based on drivers/clk/tegra/clk.h
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#ifndef __SOCFPGA_CLK_H
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#define __SOCFPGA_CLK_H
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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/* Clock Manager offsets */
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#define CLKMGR_CTRL 0x0
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#define CLKMGR_BYPASS 0x4
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#define CLKMGR_L4SRC 0x70
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#define CLKMGR_PERPLL_SRC 0xAC
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#define SOCFPGA_MAX_PARENTS 3
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#define div_mask(width) ((1 << (width)) - 1)
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extern void __iomem *clk_mgr_base_addr;
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void __init socfpga_pll_init(struct device_node *node);
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void __init socfpga_periph_init(struct device_node *node);
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void __init socfpga_gate_init(struct device_node *node);
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struct socfpga_pll {
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struct clk_gate hw;
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};
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struct socfpga_gate_clk {
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struct clk_gate hw;
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char *parent_name;
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u32 fixed_div;
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void __iomem *div_reg;
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u32 width; /* only valid if div_reg != 0 */
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u32 shift; /* only valid if div_reg != 0 */
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u32 clk_phase[2];
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};
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struct socfpga_periph_clk {
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struct clk_gate hw;
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char *parent_name;
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u32 fixed_div;
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void __iomem *div_reg;
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u32 width; /* only valid if div_reg != 0 */
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u32 shift; /* only valid if div_reg != 0 */
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};
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#endif /* SOCFPGA_CLK_H */
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