d1bef4ed5f
This patch-queue improves the generic IRQ layer to be truly generic, by adding various abstractions and features to it, without impacting existing functionality. While the queue can be best described as "fix and improve everything in the generic IRQ layer that we could think of", and thus it consists of many smaller features and lots of cleanups, the one feature that stands out most is the new 'irq chip' abstraction. The irq-chip abstraction is about describing and coding and IRQ controller driver by mapping its raw hardware capabilities [and quirks, if needed] in a straightforward way, without having to think about "IRQ flow" (level/edge/etc.) type of details. This stands in contrast with the current 'irq-type' model of genirq architectures, which 'mixes' raw hardware capabilities with 'flow' details. The patchset supports both types of irq controller designs at once, and converts i386 and x86_64 to the new irq-chip design. As a bonus side-effect of the irq-chip approach, chained interrupt controllers (master/slave PIC constructs, etc.) are now supported by design as well. The end result of this patchset intends to be simpler architecture-level code and more consolidation between architectures. We reused many bits of code and many concepts from Russell King's ARM IRQ layer, the merging of which was one of the motivations for this patchset. This patch: rename desc->handler to desc->chip. Originally i did not want to do this, because it's a big patch. But having both "desc->handler", "desc->handle_irq" and "action->handler" caused a large degree of confusion and made the code appear alot less clean than it truly is. I have also attempted a dual approach as well by introducing a desc->chip alias - but that just wasnt robust enough and broke frequently. So lets get over with this quickly. The conversion was done automatically via scripts and converts all the code in the kernel. This renaming patch is the first one amongst the patches, so that the remaining patches can stay flexible and can be merged and split up without having some big monolithic patch act as a merge barrier. [akpm@osdl.org: build fix] [akpm@osdl.org: another build fix] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
158 lines
3.3 KiB
C
158 lines
3.3 KiB
C
/*
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* linux/arch/mips/dec/ioasic-irq.c
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*
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* DEC I/O ASIC interrupts.
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*
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* Copyright (c) 2002, 2003 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <asm/dec/ioasic.h>
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#include <asm/dec/ioasic_addrs.h>
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#include <asm/dec/ioasic_ints.h>
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static DEFINE_SPINLOCK(ioasic_lock);
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static int ioasic_irq_base;
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static inline void unmask_ioasic_irq(unsigned int irq)
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{
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u32 simr;
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simr = ioasic_read(IO_REG_SIMR);
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simr |= (1 << (irq - ioasic_irq_base));
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ioasic_write(IO_REG_SIMR, simr);
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}
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static inline void mask_ioasic_irq(unsigned int irq)
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{
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u32 simr;
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simr = ioasic_read(IO_REG_SIMR);
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simr &= ~(1 << (irq - ioasic_irq_base));
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ioasic_write(IO_REG_SIMR, simr);
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}
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static inline void clear_ioasic_irq(unsigned int irq)
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{
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u32 sir;
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sir = ~(1 << (irq - ioasic_irq_base));
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ioasic_write(IO_REG_SIR, sir);
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}
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static inline void enable_ioasic_irq(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&ioasic_lock, flags);
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unmask_ioasic_irq(irq);
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spin_unlock_irqrestore(&ioasic_lock, flags);
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}
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static inline void disable_ioasic_irq(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&ioasic_lock, flags);
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mask_ioasic_irq(irq);
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spin_unlock_irqrestore(&ioasic_lock, flags);
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}
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static inline unsigned int startup_ioasic_irq(unsigned int irq)
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{
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enable_ioasic_irq(irq);
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return 0;
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}
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#define shutdown_ioasic_irq disable_ioasic_irq
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static inline void ack_ioasic_irq(unsigned int irq)
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{
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spin_lock(&ioasic_lock);
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mask_ioasic_irq(irq);
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spin_unlock(&ioasic_lock);
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fast_iob();
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}
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static inline void end_ioasic_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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enable_ioasic_irq(irq);
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}
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static struct hw_interrupt_type ioasic_irq_type = {
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.typename = "IO-ASIC",
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.startup = startup_ioasic_irq,
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.shutdown = shutdown_ioasic_irq,
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.enable = enable_ioasic_irq,
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.disable = disable_ioasic_irq,
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.ack = ack_ioasic_irq,
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.end = end_ioasic_irq,
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};
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#define startup_ioasic_dma_irq startup_ioasic_irq
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#define shutdown_ioasic_dma_irq shutdown_ioasic_irq
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#define enable_ioasic_dma_irq enable_ioasic_irq
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#define disable_ioasic_dma_irq disable_ioasic_irq
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#define ack_ioasic_dma_irq ack_ioasic_irq
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static inline void end_ioasic_dma_irq(unsigned int irq)
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{
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clear_ioasic_irq(irq);
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fast_iob();
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end_ioasic_irq(irq);
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}
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static struct hw_interrupt_type ioasic_dma_irq_type = {
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.typename = "IO-ASIC-DMA",
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.startup = startup_ioasic_dma_irq,
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.shutdown = shutdown_ioasic_dma_irq,
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.enable = enable_ioasic_dma_irq,
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.disable = disable_ioasic_dma_irq,
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.ack = ack_ioasic_dma_irq,
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.end = end_ioasic_dma_irq,
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};
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void __init init_ioasic_irqs(int base)
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{
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int i;
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/* Mask interrupts. */
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ioasic_write(IO_REG_SIMR, 0);
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fast_iob();
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for (i = base; i < base + IO_INR_DMA; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &ioasic_irq_type;
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}
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for (; i < base + IO_IRQ_LINES; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &ioasic_dma_irq_type;
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}
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ioasic_irq_base = base;
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}
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