72c35543f8
This implements preliminary support for the L2 caches found on newer SH-4A CPUs. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
25 lines
900 B
C
25 lines
900 B
C
#ifndef __ASM_SH_CPU_FEATURES_H
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#define __ASM_SH_CPU_FEATURES_H
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/*
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* Processor flags
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*
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* Note: When adding a new flag, keep cpu_flags[] in
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* arch/sh/kernel/setup.c in sync so symbolic name
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* mapping of the processor flags has a chance of being
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* reasonably accurate.
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*
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* These flags are also available through the ELF
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* auxiliary vector as AT_HWCAP.
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*/
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#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */
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#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
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#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */
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#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
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#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
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#define CPU_HAS_PTEA 0x0020 /* PTEA register */
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#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
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#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */
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#endif /* __ASM_SH_CPU_FEATURES_H */
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