027e56e685
We need to know the CPU ID in order to calculate the mask and ack registers effectively. Stub this in for UP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
87 lines
2.4 KiB
C
87 lines
2.4 KiB
C
/*
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* Interrupt handling for INTC2-based IRQ.
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*
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* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
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* Copyright (C) 2005, 2006 Paul Mundt (lethal@linux-sh.org)
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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* These are the "new Hitachi style" interrupts, as present on the
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* Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/smp.h>
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static inline struct intc2_desc *get_intc2_desc(unsigned int irq)
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{
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struct irq_chip *chip = get_irq_chip(irq);
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return (void *)((char *)chip - offsetof(struct intc2_desc, chip));
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}
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static void disable_intc2_irq(unsigned int irq)
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{
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struct intc2_data *p = get_irq_chip_data(irq);
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struct intc2_desc *d = get_intc2_desc(irq);
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ctrl_outl(1 << p->msk_shift, d->msk_base + p->msk_offset +
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(hard_smp_processor_id() * 4));
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}
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static void enable_intc2_irq(unsigned int irq)
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{
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struct intc2_data *p = get_irq_chip_data(irq);
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struct intc2_desc *d = get_intc2_desc(irq);
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ctrl_outl(1 << p->msk_shift, d->mskclr_base + p->msk_offset +
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(hard_smp_processor_id() * 4));
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}
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/*
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* Setup an INTC2 style interrupt.
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* NOTE: Unlike IPR interrupts, parameters are not shifted by this code,
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* allowing the use of the numbers straight out of the datasheet.
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* For example:
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* PIO1 which is INTPRI00[19,16] and INTMSK00[13]
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* would be: ^ ^ ^ ^
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* | | | |
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* { 84, 0, 16, 0, 13 },
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*
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* in the intc2_data table.
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*/
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void register_intc2_controller(struct intc2_desc *desc)
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{
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int i;
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desc->chip.mask = disable_intc2_irq;
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desc->chip.unmask = enable_intc2_irq;
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desc->chip.mask_ack = disable_intc2_irq;
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for (i = 0; i < desc->nr_irqs; i++) {
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unsigned long ipr, flags;
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struct intc2_data *p = desc->intc2_data + i;
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disable_irq_nosync(p->irq);
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if (desc->prio_base) {
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/* Set the priority level */
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local_irq_save(flags);
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ipr = ctrl_inl(desc->prio_base + p->ipr_offset);
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ipr &= ~(0xf << p->ipr_shift);
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ipr |= p->priority << p->ipr_shift;
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ctrl_outl(ipr, desc->prio_base + p->ipr_offset);
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local_irq_restore(flags);
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}
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set_irq_chip_and_handler_name(p->irq, &desc->chip,
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handle_level_irq, "level");
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set_irq_chip_data(p->irq, p);
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disable_intc2_irq(p->irq);
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}
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}
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