f189e14cc4
Remove superfluous volatile prefix in the communication struct definition. This eventually fixes the compile warnings with the recent gcc, too. Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
694 lines
20 KiB
C
694 lines
20 KiB
C
/****************************************************************************
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Copyright Echo Digital Audio Corporation (c) 1998 - 2004
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All rights reserved
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www.echoaudio.com
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This file is part of Echo Digital Audio's generic driver library.
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Echo Digital Audio's generic driver library is free software;
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you can redistribute it and/or modify it under the terms of
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the GNU General Public License as published by the Free Software
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Foundation.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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MA 02111-1307, USA.
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*************************************************************************
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Translation from C++ and adaptation for use in ALSA-Driver
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were made by Giuliano Pochini <pochini@shiny.it>
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****************************************************************************/
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#ifndef _ECHO_DSP_
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#define _ECHO_DSP_
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/**** Echogals: Darla20, Gina20, Layla20, and Darla24 ****/
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#if defined(ECHOGALS_FAMILY)
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#define NUM_ASIC_TESTS 5
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#define READ_DSP_TIMEOUT 1000000L /* one second */
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/**** Echo24: Gina24, Layla24, Mona, Mia, Mia-midi ****/
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#elif defined(ECHO24_FAMILY)
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#define DSP_56361 /* Some Echo24 cards use the 56361 DSP */
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#define READ_DSP_TIMEOUT 100000L /* .1 second */
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/**** 3G: Gina3G, Layla3G ****/
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#elif defined(ECHO3G_FAMILY)
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#define DSP_56361
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#define READ_DSP_TIMEOUT 100000L /* .1 second */
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#define MIN_MTC_1X_RATE 32000
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/**** Indigo: Indigo, Indigo IO, Indigo DJ ****/
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#elif defined(INDIGO_FAMILY)
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#define DSP_56361
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#define READ_DSP_TIMEOUT 100000L /* .1 second */
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#else
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#error No family is defined
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#endif
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/*
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*
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* Max inputs and outputs
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*
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*/
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#define DSP_MAXAUDIOINPUTS 16 /* Max audio input channels */
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#define DSP_MAXAUDIOOUTPUTS 16 /* Max audio output channels */
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#define DSP_MAXPIPES 32 /* Max total pipes (input + output) */
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/*
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*
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* These are the offsets for the memory-mapped DSP registers; the DSP base
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* address is treated as the start of a u32 array.
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*/
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#define CHI32_CONTROL_REG 4
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#define CHI32_STATUS_REG 5
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#define CHI32_VECTOR_REG 6
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#define CHI32_DATA_REG 7
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/*
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*
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* Interesting bits within the DSP registers
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*
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*/
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#define CHI32_VECTOR_BUSY 0x00000001
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#define CHI32_STATUS_REG_HF3 0x00000008
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#define CHI32_STATUS_REG_HF4 0x00000010
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#define CHI32_STATUS_REG_HF5 0x00000020
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#define CHI32_STATUS_HOST_READ_FULL 0x00000004
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#define CHI32_STATUS_HOST_WRITE_EMPTY 0x00000002
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#define CHI32_STATUS_IRQ 0x00000040
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/*
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*
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* DSP commands sent via slave mode; these are sent to the DSP by write_dsp()
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*
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*/
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#define DSP_FNC_SET_COMMPAGE_ADDR 0x02
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#define DSP_FNC_LOAD_LAYLA_ASIC 0xa0
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#define DSP_FNC_LOAD_GINA24_ASIC 0xa0
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#define DSP_FNC_LOAD_MONA_PCI_CARD_ASIC 0xa0
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#define DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC 0xa0
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#define DSP_FNC_LOAD_MONA_EXTERNAL_ASIC 0xa1
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#define DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC 0xa1
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#define DSP_FNC_LOAD_3G_ASIC 0xa0
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/*
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*
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* Defines to handle the MIDI input state engine; these are used to properly
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* extract MIDI time code bytes and their timestamps from the MIDI input stream.
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*
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*/
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#define MIDI_IN_STATE_NORMAL 0
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#define MIDI_IN_STATE_TS_HIGH 1
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#define MIDI_IN_STATE_TS_LOW 2
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#define MIDI_IN_STATE_F1_DATA 3
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#define MIDI_IN_SKIP_DATA (-1)
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/*----------------------------------------------------------------------------
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Setting the sample rates on Layla24 is somewhat schizophrenic.
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For standard rates, it works exactly like Mona and Gina24. That is, for
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8, 11.025, 16, 22.05, 32, 44.1, 48, 88.2, and 96 kHz, you just set the
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appropriate bits in the control register and write the control register.
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In order to support MIDI time code sync (and possibly SMPTE LTC sync in
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the future), Layla24 also has "continuous sample rate mode". In this mode,
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Layla24 can generate any sample rate between 25 and 50 kHz inclusive, or
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50 to 100 kHz inclusive for double speed mode.
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To use continuous mode:
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-Set the clock select bits in the control register to 0xe (see the #define
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below)
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-Set double-speed mode if you want to use sample rates above 50 kHz
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-Write the control register as you would normally
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-Now, you need to set the frequency register. First, you need to determine the
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value for the frequency register. This is given by the following formula:
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frequency_reg = (LAYLA24_MAGIC_NUMBER / sample_rate) - 2
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Note the #define below for the magic number
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-Wait for the DSP handshake
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-Write the frequency_reg value to the .SampleRate field of the comm page
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-Send the vector command SET_LAYLA24_FREQUENCY_REG (see vmonkey.h)
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Once you have set the control register up for continuous mode, you can just
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write the frequency register to change the sample rate. This could be
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used for MIDI time code sync. For MTC sync, the control register is set for
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continuous mode. The driver then just keeps writing the
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SET_LAYLA24_FREQUENCY_REG command.
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-----------------------------------------------------------------------------*/
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#define LAYLA24_MAGIC_NUMBER 677376000
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#define LAYLA24_CONTINUOUS_CLOCK 0x000e
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/*
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*
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* DSP vector commands
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*
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*/
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#define DSP_VC_RESET 0x80ff
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#ifndef DSP_56361
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#define DSP_VC_ACK_INT 0x8073
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#define DSP_VC_SET_VMIXER_GAIN 0x0000 /* Not used, only for compile */
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#define DSP_VC_START_TRANSFER 0x0075 /* Handshke rqd. */
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#define DSP_VC_METERS_ON 0x0079
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#define DSP_VC_METERS_OFF 0x007b
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#define DSP_VC_UPDATE_OUTVOL 0x007d /* Handshke rqd. */
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#define DSP_VC_UPDATE_INGAIN 0x007f /* Handshke rqd. */
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#define DSP_VC_ADD_AUDIO_BUFFER 0x0081 /* Handshke rqd. */
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#define DSP_VC_TEST_ASIC 0x00eb
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#define DSP_VC_UPDATE_CLOCKS 0x00ef /* Handshke rqd. */
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#define DSP_VC_SET_LAYLA_SAMPLE_RATE 0x00f1 /* Handshke rqd. */
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#define DSP_VC_SET_GD_AUDIO_STATE 0x00f1 /* Handshke rqd. */
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#define DSP_VC_WRITE_CONTROL_REG 0x00f1 /* Handshke rqd. */
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#define DSP_VC_MIDI_WRITE 0x00f5 /* Handshke rqd. */
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#define DSP_VC_STOP_TRANSFER 0x00f7 /* Handshke rqd. */
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#define DSP_VC_UPDATE_FLAGS 0x00fd /* Handshke rqd. */
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#define DSP_VC_GO_COMATOSE 0x00f9
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#else /* !DSP_56361 */
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/* Vector commands for families that use either the 56301 or 56361 */
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#define DSP_VC_ACK_INT 0x80F5
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#define DSP_VC_SET_VMIXER_GAIN 0x00DB /* Handshke rqd. */
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#define DSP_VC_START_TRANSFER 0x00DD /* Handshke rqd. */
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#define DSP_VC_METERS_ON 0x00EF
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#define DSP_VC_METERS_OFF 0x00F1
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#define DSP_VC_UPDATE_OUTVOL 0x00E3 /* Handshke rqd. */
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#define DSP_VC_UPDATE_INGAIN 0x00E5 /* Handshke rqd. */
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#define DSP_VC_ADD_AUDIO_BUFFER 0x00E1 /* Handshke rqd. */
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#define DSP_VC_TEST_ASIC 0x00ED
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#define DSP_VC_UPDATE_CLOCKS 0x00E9 /* Handshke rqd. */
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#define DSP_VC_SET_LAYLA24_FREQUENCY_REG 0x00E9 /* Handshke rqd. */
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#define DSP_VC_SET_LAYLA_SAMPLE_RATE 0x00EB /* Handshke rqd. */
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#define DSP_VC_SET_GD_AUDIO_STATE 0x00EB /* Handshke rqd. */
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#define DSP_VC_WRITE_CONTROL_REG 0x00EB /* Handshke rqd. */
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#define DSP_VC_MIDI_WRITE 0x00E7 /* Handshke rqd. */
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#define DSP_VC_STOP_TRANSFER 0x00DF /* Handshke rqd. */
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#define DSP_VC_UPDATE_FLAGS 0x00FB /* Handshke rqd. */
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#define DSP_VC_GO_COMATOSE 0x00d9
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#endif /* !DSP_56361 */
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/*
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*
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* Timeouts
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*
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*/
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#define HANDSHAKE_TIMEOUT 20000 /* send_vector command timeout (20ms) */
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#define VECTOR_BUSY_TIMEOUT 100000 /* 100ms */
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#define MIDI_OUT_DELAY_USEC 2000 /* How long to wait after MIDI fills up */
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/*
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*
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* Flags for .Flags field in the comm page
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*
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*/
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#define DSP_FLAG_MIDI_INPUT 0x0001 /* Enable MIDI input */
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#define DSP_FLAG_SPDIF_NONAUDIO 0x0002 /* Sets the "non-audio" bit
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* in the S/PDIF out status
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* bits. Clear this flag for
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* audio data;
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* set it for AC3 or WMA or
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* some such */
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#define DSP_FLAG_PROFESSIONAL_SPDIF 0x0008 /* 1 Professional, 0 Consumer */
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/*
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*
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* Clock detect bits reported by the DSP for Gina20, Layla20, Darla24, and Mia
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*
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*/
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#define GLDM_CLOCK_DETECT_BIT_WORD 0x0002
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#define GLDM_CLOCK_DETECT_BIT_SUPER 0x0004
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#define GLDM_CLOCK_DETECT_BIT_SPDIF 0x0008
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#define GLDM_CLOCK_DETECT_BIT_ESYNC 0x0010
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/*
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*
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* Clock detect bits reported by the DSP for Gina24, Mona, and Layla24
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*
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*/
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#define GML_CLOCK_DETECT_BIT_WORD96 0x0002
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#define GML_CLOCK_DETECT_BIT_WORD48 0x0004
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#define GML_CLOCK_DETECT_BIT_SPDIF48 0x0008
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#define GML_CLOCK_DETECT_BIT_SPDIF96 0x0010
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#define GML_CLOCK_DETECT_BIT_WORD (GML_CLOCK_DETECT_BIT_WORD96 | GML_CLOCK_DETECT_BIT_WORD48)
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#define GML_CLOCK_DETECT_BIT_SPDIF (GML_CLOCK_DETECT_BIT_SPDIF48 | GML_CLOCK_DETECT_BIT_SPDIF96)
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#define GML_CLOCK_DETECT_BIT_ESYNC 0x0020
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#define GML_CLOCK_DETECT_BIT_ADAT 0x0040
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/*
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*
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* Layla clock numbers to send to DSP
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*
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*/
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#define LAYLA20_CLOCK_INTERNAL 0
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#define LAYLA20_CLOCK_SPDIF 1
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#define LAYLA20_CLOCK_WORD 2
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#define LAYLA20_CLOCK_SUPER 3
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/*
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*
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* Gina/Darla clock states
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*
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*/
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#define GD_CLOCK_NOCHANGE 0
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#define GD_CLOCK_44 1
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#define GD_CLOCK_48 2
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#define GD_CLOCK_SPDIFIN 3
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#define GD_CLOCK_UNDEF 0xff
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/*
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*
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* Gina/Darla S/PDIF status bits
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*
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*/
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#define GD_SPDIF_STATUS_NOCHANGE 0
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#define GD_SPDIF_STATUS_44 1
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#define GD_SPDIF_STATUS_48 2
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#define GD_SPDIF_STATUS_UNDEF 0xff
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/*
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*
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* Layla20 output clocks
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*
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*/
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#define LAYLA20_OUTPUT_CLOCK_SUPER 0
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#define LAYLA20_OUTPUT_CLOCK_WORD 1
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/****************************************************************************
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Magic constants for the Darla24 hardware
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****************************************************************************/
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#define GD24_96000 0x0
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#define GD24_48000 0x1
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#define GD24_44100 0x2
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#define GD24_32000 0x3
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#define GD24_22050 0x4
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#define GD24_16000 0x5
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#define GD24_11025 0x6
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#define GD24_8000 0x7
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#define GD24_88200 0x8
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#define GD24_EXT_SYNC 0x9
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/*
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*
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* Return values from the DSP when ASIC is loaded
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*
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*/
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#define ASIC_ALREADY_LOADED 0x1
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#define ASIC_NOT_LOADED 0x0
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/*
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*
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* DSP Audio formats
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*
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* These are the audio formats that the DSP can transfer
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* via input and output pipes. LE means little-endian,
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* BE means big-endian.
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*
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* DSP_AUDIOFORM_MS_8
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*
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* 8-bit mono unsigned samples. For playback,
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* mono data is duplicated out the left and right channels
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* of the output bus. The "MS" part of the name
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* means mono->stereo.
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*
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* DSP_AUDIOFORM_MS_16LE
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*
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* 16-bit signed little-endian mono samples. Playback works
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* like the previous code.
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*
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* DSP_AUDIOFORM_MS_24LE
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*
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* 24-bit signed little-endian mono samples. Data is packed
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* three bytes per sample; if you had two samples 0x112233 and 0x445566
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* they would be stored in memory like this: 33 22 11 66 55 44.
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*
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* DSP_AUDIOFORM_MS_32LE
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*
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* 24-bit signed little-endian mono samples in a 32-bit
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* container. In other words, each sample is a 32-bit signed
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* integer, where the actual audio data is left-justified
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* in the 32 bits and only the 24 most significant bits are valid.
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*
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* DSP_AUDIOFORM_SS_8
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* DSP_AUDIOFORM_SS_16LE
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* DSP_AUDIOFORM_SS_24LE
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* DSP_AUDIOFORM_SS_32LE
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*
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* Like the previous ones, except now with stereo interleaved
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* data. "SS" means stereo->stereo.
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*
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* DSP_AUDIOFORM_MM_32LE
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*
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* Similar to DSP_AUDIOFORM_MS_32LE, except that the mono
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* data is not duplicated out both the left and right outputs.
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* This mode is used by the ASIO driver. Here, "MM" means
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* mono->mono.
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*
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* DSP_AUDIOFORM_MM_32BE
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*
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* Just like DSP_AUDIOFORM_MM_32LE, but now the data is
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* in big-endian format.
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*
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*/
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#define DSP_AUDIOFORM_MS_8 0 /* 8 bit mono */
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#define DSP_AUDIOFORM_MS_16LE 1 /* 16 bit mono */
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#define DSP_AUDIOFORM_MS_24LE 2 /* 24 bit mono */
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#define DSP_AUDIOFORM_MS_32LE 3 /* 32 bit mono */
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#define DSP_AUDIOFORM_SS_8 4 /* 8 bit stereo */
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#define DSP_AUDIOFORM_SS_16LE 5 /* 16 bit stereo */
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#define DSP_AUDIOFORM_SS_24LE 6 /* 24 bit stereo */
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#define DSP_AUDIOFORM_SS_32LE 7 /* 32 bit stereo */
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#define DSP_AUDIOFORM_MM_32LE 8 /* 32 bit mono->mono little-endian */
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#define DSP_AUDIOFORM_MM_32BE 9 /* 32 bit mono->mono big-endian */
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#define DSP_AUDIOFORM_SS_32BE 10 /* 32 bit stereo big endian */
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#define DSP_AUDIOFORM_INVALID 0xFF /* Invalid audio format */
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/*
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*
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* Super-interleave is defined as interleaving by 4 or more. Darla20 and Gina20
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* do not support super interleave.
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*
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* 16 bit, 24 bit, and 32 bit little endian samples are supported for super
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* interleave. The interleave factor must be even. 16 - way interleave is the
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* current maximum, so you can interleave by 4, 6, 8, 10, 12, 14, and 16.
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*
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* The actual format code is derived by taking the define below and or-ing with
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* the interleave factor. So, 32 bit interleave by 6 is 0x86 and
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* 16 bit interleave by 16 is (0x40 | 0x10) = 0x50.
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*
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*/
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#define DSP_AUDIOFORM_SUPER_INTERLEAVE_16LE 0x40
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#define DSP_AUDIOFORM_SUPER_INTERLEAVE_24LE 0xc0
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#define DSP_AUDIOFORM_SUPER_INTERLEAVE_32LE 0x80
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/*
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*
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* Gina24, Mona, and Layla24 control register defines
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*
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*/
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#define GML_CONVERTER_ENABLE 0x0010
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#define GML_SPDIF_PRO_MODE 0x0020 /* Professional S/PDIF == 1,
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consumer == 0 */
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#define GML_SPDIF_SAMPLE_RATE0 0x0040
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#define GML_SPDIF_SAMPLE_RATE1 0x0080
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#define GML_SPDIF_TWO_CHANNEL 0x0100 /* 1 == two channels,
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0 == one channel */
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#define GML_SPDIF_NOT_AUDIO 0x0200
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#define GML_SPDIF_COPY_PERMIT 0x0400
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#define GML_SPDIF_24_BIT 0x0800 /* 1 == 24 bit, 0 == 20 bit */
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#define GML_ADAT_MODE 0x1000 /* 1 == ADAT mode, 0 == S/PDIF mode */
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#define GML_SPDIF_OPTICAL_MODE 0x2000 /* 1 == optical mode, 0 == RCA mode */
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#define GML_SPDIF_CDROM_MODE 0x3000 /* 1 == CDROM mode,
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* 0 == RCA or optical mode */
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#define GML_DOUBLE_SPEED_MODE 0x4000 /* 1 == double speed,
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0 == single speed */
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#define GML_DIGITAL_IN_AUTO_MUTE 0x800000
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#define GML_96KHZ (0x0 | GML_DOUBLE_SPEED_MODE)
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#define GML_88KHZ (0x1 | GML_DOUBLE_SPEED_MODE)
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#define GML_48KHZ 0x2
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#define GML_44KHZ 0x3
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#define GML_32KHZ 0x4
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#define GML_22KHZ 0x5
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#define GML_16KHZ 0x6
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#define GML_11KHZ 0x7
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#define GML_8KHZ 0x8
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#define GML_SPDIF_CLOCK 0x9
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#define GML_ADAT_CLOCK 0xA
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#define GML_WORD_CLOCK 0xB
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#define GML_ESYNC_CLOCK 0xC
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#define GML_ESYNCx2_CLOCK 0xD
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#define GML_CLOCK_CLEAR_MASK 0xffffbff0
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#define GML_SPDIF_RATE_CLEAR_MASK (~(GML_SPDIF_SAMPLE_RATE0|GML_SPDIF_SAMPLE_RATE1))
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#define GML_DIGITAL_MODE_CLEAR_MASK 0xffffcfff
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#define GML_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f
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|
|
|
|
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/*
|
|
*
|
|
* Mia sample rate and clock setting constants
|
|
*
|
|
*/
|
|
|
|
#define MIA_32000 0x0040
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#define MIA_44100 0x0042
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#define MIA_48000 0x0041
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#define MIA_88200 0x0142
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#define MIA_96000 0x0141
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|
|
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#define MIA_SPDIF 0x00000044
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#define MIA_SPDIF96 0x00000144
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|
|
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#define MIA_MIDI_REV 1 /* Must be Mia rev 1 for MIDI support */
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|
|
|
|
|
/*
|
|
*
|
|
* 3G register bits
|
|
*
|
|
*/
|
|
|
|
#define E3G_CONVERTER_ENABLE 0x0010
|
|
#define E3G_SPDIF_PRO_MODE 0x0020 /* Professional S/PDIF == 1,
|
|
consumer == 0 */
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|
#define E3G_SPDIF_SAMPLE_RATE0 0x0040
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|
#define E3G_SPDIF_SAMPLE_RATE1 0x0080
|
|
#define E3G_SPDIF_TWO_CHANNEL 0x0100 /* 1 == two channels,
|
|
0 == one channel */
|
|
#define E3G_SPDIF_NOT_AUDIO 0x0200
|
|
#define E3G_SPDIF_COPY_PERMIT 0x0400
|
|
#define E3G_SPDIF_24_BIT 0x0800 /* 1 == 24 bit, 0 == 20 bit */
|
|
#define E3G_DOUBLE_SPEED_MODE 0x4000 /* 1 == double speed,
|
|
0 == single speed */
|
|
#define E3G_PHANTOM_POWER 0x8000 /* 1 == phantom power on,
|
|
0 == phantom power off */
|
|
|
|
#define E3G_96KHZ (0x0 | E3G_DOUBLE_SPEED_MODE)
|
|
#define E3G_88KHZ (0x1 | E3G_DOUBLE_SPEED_MODE)
|
|
#define E3G_48KHZ 0x2
|
|
#define E3G_44KHZ 0x3
|
|
#define E3G_32KHZ 0x4
|
|
#define E3G_22KHZ 0x5
|
|
#define E3G_16KHZ 0x6
|
|
#define E3G_11KHZ 0x7
|
|
#define E3G_8KHZ 0x8
|
|
#define E3G_SPDIF_CLOCK 0x9
|
|
#define E3G_ADAT_CLOCK 0xA
|
|
#define E3G_WORD_CLOCK 0xB
|
|
#define E3G_CONTINUOUS_CLOCK 0xE
|
|
|
|
#define E3G_ADAT_MODE 0x1000
|
|
#define E3G_SPDIF_OPTICAL_MODE 0x2000
|
|
|
|
#define E3G_CLOCK_CLEAR_MASK 0xbfffbff0
|
|
#define E3G_DIGITAL_MODE_CLEAR_MASK 0xffffcfff
|
|
#define E3G_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f
|
|
|
|
/* Clock detect bits reported by the DSP */
|
|
#define E3G_CLOCK_DETECT_BIT_WORD96 0x0001
|
|
#define E3G_CLOCK_DETECT_BIT_WORD48 0x0002
|
|
#define E3G_CLOCK_DETECT_BIT_SPDIF48 0x0004
|
|
#define E3G_CLOCK_DETECT_BIT_ADAT 0x0004
|
|
#define E3G_CLOCK_DETECT_BIT_SPDIF96 0x0008
|
|
#define E3G_CLOCK_DETECT_BIT_WORD (E3G_CLOCK_DETECT_BIT_WORD96|E3G_CLOCK_DETECT_BIT_WORD48)
|
|
#define E3G_CLOCK_DETECT_BIT_SPDIF (E3G_CLOCK_DETECT_BIT_SPDIF48|E3G_CLOCK_DETECT_BIT_SPDIF96)
|
|
|
|
/* Frequency control register */
|
|
#define E3G_MAGIC_NUMBER 677376000
|
|
#define E3G_FREQ_REG_DEFAULT (E3G_MAGIC_NUMBER / 48000 - 2)
|
|
#define E3G_FREQ_REG_MAX 0xffff
|
|
|
|
/* 3G external box types */
|
|
#define E3G_GINA3G_BOX_TYPE 0x00
|
|
#define E3G_LAYLA3G_BOX_TYPE 0x10
|
|
#define E3G_ASIC_NOT_LOADED 0xffff
|
|
#define E3G_BOX_TYPE_MASK 0xf0
|
|
|
|
#define EXT_3GBOX_NC 0x01
|
|
#define EXT_3GBOX_NOT_SET 0x02
|
|
|
|
|
|
/*
|
|
*
|
|
* Gina20 & Layla20 have input gain controls for the analog inputs;
|
|
* this is the magic number for the hardware that gives you 0 dB at -10.
|
|
*
|
|
*/
|
|
|
|
#define GL20_INPUT_GAIN_MAGIC_NUMBER 0xC8
|
|
|
|
|
|
/*
|
|
*
|
|
* Defines how much time must pass between DSP load attempts
|
|
*
|
|
*/
|
|
|
|
#define DSP_LOAD_ATTEMPT_PERIOD 1000000L /* One second */
|
|
|
|
|
|
/*
|
|
*
|
|
* Size of arrays for the comm page. MAX_PLAY_TAPS and MAX_REC_TAPS are
|
|
* no longer used, but the sizes must still be right for the DSP to see
|
|
* the comm page correctly.
|
|
*
|
|
*/
|
|
|
|
#define MONITOR_ARRAY_SIZE 0x180
|
|
#define VMIXER_ARRAY_SIZE 0x40
|
|
#define MIDI_OUT_BUFFER_SIZE 32
|
|
#define MIDI_IN_BUFFER_SIZE 256
|
|
#define MAX_PLAY_TAPS 168
|
|
#define MAX_REC_TAPS 192
|
|
#define DSP_MIDI_OUT_FIFO_SIZE 64
|
|
|
|
|
|
/* sg_entry is a single entry for the scatter-gather list. The array of struct
|
|
sg_entry struct is read by the DSP, so all values must be little-endian. */
|
|
|
|
#define MAX_SGLIST_ENTRIES 512
|
|
|
|
struct sg_entry {
|
|
u32 addr;
|
|
u32 size;
|
|
};
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
The comm page. This structure is read and written by the DSP; the
|
|
DSP code is a firm believer in the byte offsets written in the comments
|
|
at the end of each line. This structure should not be changed.
|
|
|
|
Any reads from or writes to this structure should be in little-endian format.
|
|
|
|
****************************************************************************/
|
|
|
|
struct comm_page { /* Base Length*/
|
|
u32 comm_size; /* size of this object 0x000 4 */
|
|
u32 flags; /* See Appendix A below 0x004 4 */
|
|
u32 unused; /* Unused entry 0x008 4 */
|
|
u32 sample_rate; /* Card sample rate in Hz 0x00c 4 */
|
|
u32 handshake; /* DSP command handshake 0x010 4 */
|
|
u32 cmd_start; /* Chs. to start mask 0x014 4 */
|
|
u32 cmd_stop; /* Chs. to stop mask 0x018 4 */
|
|
u32 cmd_reset; /* Chs. to reset mask 0x01c 4 */
|
|
u16 audio_format[DSP_MAXPIPES]; /* Chs. audio format 0x020 32*2 */
|
|
struct sg_entry sglist_addr[DSP_MAXPIPES];
|
|
/* Chs. Physical sglist addrs 0x060 32*8 */
|
|
u32 position[DSP_MAXPIPES];
|
|
/* Positions for ea. ch. 0x160 32*4 */
|
|
s8 vu_meter[DSP_MAXPIPES];
|
|
/* VU meters 0x1e0 32*1 */
|
|
s8 peak_meter[DSP_MAXPIPES];
|
|
/* Peak meters 0x200 32*1 */
|
|
s8 line_out_level[DSP_MAXAUDIOOUTPUTS];
|
|
/* Output gain 0x220 16*1 */
|
|
s8 line_in_level[DSP_MAXAUDIOINPUTS];
|
|
/* Input gain 0x230 16*1 */
|
|
s8 monitors[MONITOR_ARRAY_SIZE];
|
|
/* Monitor map 0x240 0x180 */
|
|
u32 play_coeff[MAX_PLAY_TAPS];
|
|
/* Gina/Darla play filters - obsolete 0x3c0 168*4 */
|
|
u32 rec_coeff[MAX_REC_TAPS];
|
|
/* Gina/Darla record filters - obsolete 0x660 192*4 */
|
|
u16 midi_input[MIDI_IN_BUFFER_SIZE];
|
|
/* MIDI input data transfer buffer 0x960 256*2 */
|
|
u8 gd_clock_state; /* Chg Gina/Darla clock state 0xb60 1 */
|
|
u8 gd_spdif_status; /* Chg. Gina/Darla S/PDIF state 0xb61 1 */
|
|
u8 gd_resampler_state; /* Should always be 3 0xb62 1 */
|
|
u8 filler2; /* 0xb63 1 */
|
|
u32 nominal_level_mask; /* -10 level enable mask 0xb64 4 */
|
|
u16 input_clock; /* Chg. Input clock state 0xb68 2 */
|
|
u16 output_clock; /* Chg. Output clock state 0xb6a 2 */
|
|
u32 status_clocks; /* Current Input clock state 0xb6c 4 */
|
|
u32 ext_box_status; /* External box status 0xb70 4 */
|
|
u32 cmd_add_buffer; /* Pipes to add (obsolete) 0xb74 4 */
|
|
u32 midi_out_free_count;
|
|
/* # of bytes free in MIDI output FIFO 0xb78 4 */
|
|
u32 unused2; /* Cyclic pipes 0xb7c 4 */
|
|
u32 control_register;
|
|
/* Mona, Gina24, Layla24, 3G ctrl reg 0xb80 4 */
|
|
u32 e3g_frq_register; /* 3G frequency register 0xb84 4 */
|
|
u8 filler[24]; /* filler 0xb88 24*1 */
|
|
s8 vmixer[VMIXER_ARRAY_SIZE];
|
|
/* Vmixer levels 0xba0 64*1 */
|
|
u8 midi_output[MIDI_OUT_BUFFER_SIZE];
|
|
/* MIDI output data 0xbe0 32*1 */
|
|
};
|
|
|
|
#endif /* _ECHO_DSP_ */
|