70ae04e6cc
#1: sep->cache_addr is assigned to sep->rar_addr and never changed sep->rar_addr is never assigned after this point #2: sep->cache_bus ditto for sep->rar_bus #3 sep->rar_region_addr is assigned but necer used #4 sep->io_addr is in fact private to the probe function and the same as the reg_addr #5 The remainig sep->io fields are in fact function locals #6 sep->message_shared_area is assigned once from sep->shared_area sep->shared_area does not then change #7 sep->shared_addr and sep->shared_area_addr are the same thing, ditto for the bus addresses. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
111 lines
3.0 KiB
C
111 lines
3.0 KiB
C
#ifndef __SEP_DEV_H__
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#define __SEP_DEV_H__
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/*
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*
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* sep_dev.h - Security Processor Device Structures
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*
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* Copyright(c) 2009 Intel Corporation. All rights reserved.
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* Copyright(c) 2009 Discretix. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* CONTACTS:
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*
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* Alan Cox alan@linux.intel.com
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*
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*/
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struct sep_device {
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/* pointer to pci dev */
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struct pci_dev *pdev;
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unsigned long in_use;
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/* address of the shared memory allocated during init for SEP driver
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(coherent alloc) */
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void *shared_addr;
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/* the physical address of the shared area */
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dma_addr_t shared_bus;
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/* restricted access region (coherent alloc) */
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dma_addr_t rar_bus;
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void *rar_addr;
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/* firmware regions: cache is at rar_addr */
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unsigned long cache_size;
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/* follows the cache */
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dma_addr_t resident_bus;
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unsigned long resident_size;
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void *resident_addr;
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/* start address of the access to the SEP registers from driver */
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void __iomem *reg_addr;
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/* transaction counter that coordinates the transactions between SEP and HOST */
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unsigned long send_ct;
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/* counter for the messages from sep */
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unsigned long reply_ct;
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/* counter for the number of bytes allocated in the pool for the current
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transaction */
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unsigned long data_pool_bytes_allocated;
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/* array of pointers to the pages that represent input data for the synchronic
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DMA action */
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struct page **in_page_array;
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/* array of pointers to the pages that represent out data for the synchronic
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DMA action */
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struct page **out_page_array;
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/* number of pages in the sep_in_page_array */
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unsigned long in_num_pages;
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/* number of pages in the sep_out_page_array */
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unsigned long out_num_pages;
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/* global data for every flow */
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struct sep_flow_context_t flows[SEP_DRIVER_NUM_FLOWS];
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/* pointer to the workqueue that handles the flow done interrupts */
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struct workqueue_struct *flow_wq;
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};
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static struct sep_device *sep_dev;
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static inline void sep_write_reg(struct sep_device *dev, int reg, u32 value)
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{
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void __iomem *addr = dev->reg_addr + reg;
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writel(value, addr);
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}
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static inline u32 sep_read_reg(struct sep_device *dev, int reg)
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{
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void __iomem *addr = dev->reg_addr + reg;
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return readl(addr);
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}
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/* wait for SRAM write complete(indirect write */
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static inline void sep_wait_sram_write(struct sep_device *dev)
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{
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u32 reg_val;
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do
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reg_val = sep_read_reg(dev, HW_SRAM_DATA_READY_REG_ADDR);
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while (!(reg_val & 1));
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}
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#endif
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