ec977c5b47
Many of the comments didn't follow kerneldoc guidlines. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: netdev@vger.kernel.org To: gregkh@suse.de Patchwork: http://patchwork.linux-mips.org/patch/971/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
560 lines
15 KiB
C
560 lines
15 KiB
C
/**********************************************************************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2010 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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**********************************************************************/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/cache.h>
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#include <linux/cpumask.h>
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#include <linux/netdevice.h>
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#include <linux/init.h>
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#include <linux/etherdevice.h>
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#include <linux/ip.h>
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#include <linux/string.h>
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#include <linux/prefetch.h>
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#include <linux/smp.h>
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#include <net/dst.h>
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#ifdef CONFIG_XFRM
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#include <linux/xfrm.h>
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#include <net/xfrm.h>
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#endif /* CONFIG_XFRM */
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#include <asm/atomic.h>
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#include <asm/octeon/octeon.h>
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#include "ethernet-defines.h"
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#include "ethernet-mem.h"
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#include "ethernet-rx.h"
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#include "octeon-ethernet.h"
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#include "ethernet-util.h"
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#include "cvmx-helper.h"
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#include "cvmx-wqe.h"
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#include "cvmx-fau.h"
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#include "cvmx-pow.h"
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#include "cvmx-pip.h"
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#include "cvmx-scratch.h"
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#include "cvmx-gmxx-defs.h"
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struct cvm_napi_wrapper {
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struct napi_struct napi;
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} ____cacheline_aligned_in_smp;
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static struct cvm_napi_wrapper cvm_oct_napi[NR_CPUS] __cacheline_aligned_in_smp;
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struct cvm_oct_core_state {
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int baseline_cores;
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/*
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* The number of additional cores that could be processing
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* input packtes.
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*/
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atomic_t available_cores;
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cpumask_t cpu_state;
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} ____cacheline_aligned_in_smp;
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static struct cvm_oct_core_state core_state __cacheline_aligned_in_smp;
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static void cvm_oct_enable_napi(void *_)
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{
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int cpu = smp_processor_id();
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napi_schedule(&cvm_oct_napi[cpu].napi);
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}
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static void cvm_oct_enable_one_cpu(void)
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{
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int v;
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int cpu;
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/* Check to see if more CPUs are available for receive processing... */
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v = atomic_sub_if_positive(1, &core_state.available_cores);
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if (v < 0)
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return;
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/* ... if a CPU is available, Turn on NAPI polling for that CPU. */
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for_each_online_cpu(cpu) {
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if (!cpu_test_and_set(cpu, core_state.cpu_state)) {
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v = smp_call_function_single(cpu, cvm_oct_enable_napi,
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NULL, 0);
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if (v)
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panic("Can't enable NAPI.");
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break;
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}
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}
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}
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static void cvm_oct_no_more_work(void)
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{
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int cpu = smp_processor_id();
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/*
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* CPU zero is special. It always has the irq enabled when
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* waiting for incoming packets.
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*/
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if (cpu == 0) {
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enable_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group);
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return;
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}
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cpu_clear(cpu, core_state.cpu_state);
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atomic_add(1, &core_state.available_cores);
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}
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/**
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* cvm_oct_do_interrupt - interrupt handler.
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*
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* The interrupt occurs whenever the POW has packets in our group.
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*
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*/
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static irqreturn_t cvm_oct_do_interrupt(int cpl, void *dev_id)
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{
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/* Disable the IRQ and start napi_poll. */
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disable_irq_nosync(OCTEON_IRQ_WORKQ0 + pow_receive_group);
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cvm_oct_enable_napi(NULL);
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return IRQ_HANDLED;
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}
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/**
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* cvm_oct_check_rcv_error - process receive errors
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* @work: Work queue entry pointing to the packet.
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*
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* Returns Non-zero if the packet can be dropped, zero otherwise.
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*/
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static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
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{
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if ((work->word2.snoip.err_code == 10) && (work->len <= 64)) {
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/*
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* Ignore length errors on min size packets. Some
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* equipment incorrectly pads packets to 64+4FCS
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* instead of 60+4FCS. Note these packets still get
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* counted as frame errors.
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*/
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} else
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if (USE_10MBPS_PREAMBLE_WORKAROUND
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&& ((work->word2.snoip.err_code == 5)
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|| (work->word2.snoip.err_code == 7))) {
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/*
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* We received a packet with either an alignment error
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* or a FCS error. This may be signalling that we are
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* running 10Mbps with GMXX_RXX_FRM_CTL[PRE_CHK}
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* off. If this is the case we need to parse the
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* packet to determine if we can remove a non spec
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* preamble and generate a correct packet.
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*/
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int interface = cvmx_helper_get_interface_num(work->ipprt);
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int index = cvmx_helper_get_interface_index_num(work->ipprt);
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union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
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gmxx_rxx_frm_ctl.u64 =
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cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
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if (gmxx_rxx_frm_ctl.s.pre_chk == 0) {
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uint8_t *ptr =
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cvmx_phys_to_ptr(work->packet_ptr.s.addr);
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int i = 0;
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while (i < work->len - 1) {
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if (*ptr != 0x55)
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break;
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ptr++;
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i++;
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}
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if (*ptr == 0xd5) {
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/*
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DEBUGPRINT("Port %d received 0xd5 preamble\n", work->ipprt);
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*/
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work->packet_ptr.s.addr += i + 1;
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work->len -= i + 5;
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} else if ((*ptr & 0xf) == 0xd) {
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/*
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DEBUGPRINT("Port %d received 0x?d preamble\n", work->ipprt);
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*/
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work->packet_ptr.s.addr += i;
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work->len -= i + 4;
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for (i = 0; i < work->len; i++) {
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*ptr =
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((*ptr & 0xf0) >> 4) |
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((*(ptr + 1) & 0xf) << 4);
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ptr++;
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}
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} else {
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DEBUGPRINT("Port %d unknown preamble, packet "
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"dropped\n",
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work->ipprt);
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/*
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cvmx_helper_dump_packet(work);
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*/
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cvm_oct_free_work(work);
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return 1;
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}
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}
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} else {
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DEBUGPRINT("Port %d receive error code %d, packet dropped\n",
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work->ipprt, work->word2.snoip.err_code);
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cvm_oct_free_work(work);
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return 1;
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}
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return 0;
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}
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/**
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* cvm_oct_napi_poll - the NAPI poll function.
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* @napi: The NAPI instance, or null if called from cvm_oct_poll_controller
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* @budget: Maximum number of packets to receive.
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*
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* Returns the number of packets processed.
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*/
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static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
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{
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const int coreid = cvmx_get_core_num();
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uint64_t old_group_mask;
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uint64_t old_scratch;
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int rx_count = 0;
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int did_work_request = 0;
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int packet_not_copied;
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/* Prefetch cvm_oct_device since we know we need it soon */
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prefetch(cvm_oct_device);
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if (USE_ASYNC_IOBDMA) {
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/* Save scratch in case userspace is using it */
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CVMX_SYNCIOBDMA;
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old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
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}
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/* Only allow work for our group (and preserve priorities) */
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old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid));
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cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid),
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(old_group_mask & ~0xFFFFull) | 1 << pow_receive_group);
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if (USE_ASYNC_IOBDMA) {
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cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
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did_work_request = 1;
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}
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while (rx_count < budget) {
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struct sk_buff *skb = NULL;
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struct sk_buff **pskb = NULL;
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int skb_in_hw;
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cvmx_wqe_t *work;
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if (USE_ASYNC_IOBDMA && did_work_request)
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work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
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else
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work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
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prefetch(work);
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did_work_request = 0;
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if (work == NULL) {
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union cvmx_pow_wq_int wq_int;
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wq_int.u64 = 0;
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wq_int.s.iq_dis = 1 << pow_receive_group;
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wq_int.s.wq_int = 1 << pow_receive_group;
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cvmx_write_csr(CVMX_POW_WQ_INT, wq_int.u64);
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break;
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}
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pskb = (struct sk_buff **)(cvm_oct_get_buffer_ptr(work->packet_ptr) - sizeof(void *));
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prefetch(pskb);
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if (USE_ASYNC_IOBDMA && rx_count < (budget - 1)) {
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cvmx_pow_work_request_async_nocheck(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
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did_work_request = 1;
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}
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if (rx_count == 0) {
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/*
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* First time through, see if there is enough
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* work waiting to merit waking another
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* CPU.
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*/
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union cvmx_pow_wq_int_cntx counts;
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int backlog;
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int cores_in_use = core_state.baseline_cores - atomic_read(&core_state.available_cores);
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counts.u64 = cvmx_read_csr(CVMX_POW_WQ_INT_CNTX(pow_receive_group));
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backlog = counts.s.iq_cnt + counts.s.ds_cnt;
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if (backlog > budget * cores_in_use && napi != NULL)
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cvm_oct_enable_one_cpu();
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}
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skb_in_hw = USE_SKBUFFS_IN_HW && work->word2.s.bufs == 1;
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if (likely(skb_in_hw)) {
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skb = *pskb;
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prefetch(&skb->head);
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prefetch(&skb->len);
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}
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prefetch(cvm_oct_device[work->ipprt]);
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/* Immediately throw away all packets with receive errors */
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if (unlikely(work->word2.snoip.rcv_error)) {
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if (cvm_oct_check_rcv_error(work))
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continue;
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}
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/*
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* We can only use the zero copy path if skbuffs are
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* in the FPA pool and the packet fits in a single
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* buffer.
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*/
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if (likely(skb_in_hw)) {
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skb->data = skb->head + work->packet_ptr.s.addr - cvmx_ptr_to_phys(skb->head);
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prefetch(skb->data);
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skb->len = work->len;
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skb_set_tail_pointer(skb, skb->len);
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packet_not_copied = 1;
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} else {
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/*
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* We have to copy the packet. First allocate
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* an skbuff for it.
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*/
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skb = dev_alloc_skb(work->len);
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if (!skb) {
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DEBUGPRINT("Port %d failed to allocate skbuff, packet dropped\n",
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work->ipprt);
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cvm_oct_free_work(work);
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continue;
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}
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/*
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* Check if we've received a packet that was
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* entirely stored in the work entry.
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*/
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if (unlikely(work->word2.s.bufs == 0)) {
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uint8_t *ptr = work->packet_data;
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if (likely(!work->word2.s.not_IP)) {
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/*
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* The beginning of the packet
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* moves for IP packets.
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*/
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if (work->word2.s.is_v6)
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ptr += 2;
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else
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ptr += 6;
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}
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memcpy(skb_put(skb, work->len), ptr, work->len);
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/* No packet buffers to free */
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} else {
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int segments = work->word2.s.bufs;
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union cvmx_buf_ptr segment_ptr = work->packet_ptr;
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int len = work->len;
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while (segments--) {
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union cvmx_buf_ptr next_ptr =
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*(union cvmx_buf_ptr *)cvmx_phys_to_ptr(segment_ptr.s.addr - 8);
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/*
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* Octeon Errata PKI-100: The segment size is
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* wrong. Until it is fixed, calculate the
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* segment size based on the packet pool
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* buffer size. When it is fixed, the
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* following line should be replaced with this
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* one: int segment_size =
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* segment_ptr.s.size;
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*/
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int segment_size = CVMX_FPA_PACKET_POOL_SIZE -
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(segment_ptr.s.addr - (((segment_ptr.s.addr >> 7) - segment_ptr.s.back) << 7));
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/*
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* Don't copy more than what
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* is left in the packet.
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*/
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if (segment_size > len)
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segment_size = len;
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/* Copy the data into the packet */
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memcpy(skb_put(skb, segment_size),
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cvmx_phys_to_ptr(segment_ptr.s.addr),
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segment_size);
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len -= segment_size;
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segment_ptr = next_ptr;
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}
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}
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packet_not_copied = 0;
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}
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if (likely((work->ipprt < TOTAL_NUMBER_OF_PORTS) &&
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cvm_oct_device[work->ipprt])) {
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struct net_device *dev = cvm_oct_device[work->ipprt];
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struct octeon_ethernet *priv = netdev_priv(dev);
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/*
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* Only accept packets for devices that are
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* currently up.
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*/
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if (likely(dev->flags & IFF_UP)) {
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skb->protocol = eth_type_trans(skb, dev);
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skb->dev = dev;
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if (unlikely(work->word2.s.not_IP || work->word2.s.IP_exc || work->word2.s.L4_error))
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skb->ip_summed = CHECKSUM_NONE;
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else
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skb->ip_summed = CHECKSUM_UNNECESSARY;
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/* Increment RX stats for virtual ports */
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if (work->ipprt >= CVMX_PIP_NUM_INPUT_PORTS) {
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#ifdef CONFIG_64BIT
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atomic64_add(1, (atomic64_t *)&priv->stats.rx_packets);
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atomic64_add(skb->len, (atomic64_t *)&priv->stats.rx_bytes);
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#else
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atomic_add(1, (atomic_t *)&priv->stats.rx_packets);
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atomic_add(skb->len, (atomic_t *)&priv->stats.rx_bytes);
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#endif
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}
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netif_receive_skb(skb);
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rx_count++;
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} else {
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/* Drop any packet received for a device that isn't up */
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/*
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DEBUGPRINT("%s: Device not up, packet dropped\n",
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dev->name);
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*/
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#ifdef CONFIG_64BIT
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atomic64_add(1, (atomic64_t *)&priv->stats.rx_dropped);
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#else
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atomic_add(1, (atomic_t *)&priv->stats.rx_dropped);
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#endif
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dev_kfree_skb_irq(skb);
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}
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} else {
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/*
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* Drop any packet received for a device that
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* doesn't exist.
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*/
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DEBUGPRINT("Port %d not controlled by Linux, packet dropped\n",
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work->ipprt);
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dev_kfree_skb_irq(skb);
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}
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/*
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* Check to see if the skbuff and work share the same
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* packet buffer.
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*/
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if (USE_SKBUFFS_IN_HW && likely(packet_not_copied)) {
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/*
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* This buffer needs to be replaced, increment
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* the number of buffers we need to free by
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* one.
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*/
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cvmx_fau_atomic_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE,
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1);
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cvmx_fpa_free(work, CVMX_FPA_WQE_POOL,
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DONT_WRITEBACK(1));
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} else {
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cvm_oct_free_work(work);
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}
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}
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/* Restore the original POW group mask */
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cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
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if (USE_ASYNC_IOBDMA) {
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/* Restore the scratch area */
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cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
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}
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cvm_oct_rx_refill_pool(0);
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if (rx_count < budget && napi != NULL) {
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/* No more work */
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napi_complete(napi);
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cvm_oct_no_more_work();
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}
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return rx_count;
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}
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|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
/**
|
|
* cvm_oct_poll_controller - poll for receive packets
|
|
* device.
|
|
*
|
|
* @dev: Device to poll. Unused
|
|
*/
|
|
void cvm_oct_poll_controller(struct net_device *dev)
|
|
{
|
|
cvm_oct_napi_poll(NULL, 16);
|
|
}
|
|
#endif
|
|
|
|
void cvm_oct_rx_initialize(void)
|
|
{
|
|
int i;
|
|
struct net_device *dev_for_napi = NULL;
|
|
union cvmx_pow_wq_int_thrx int_thr;
|
|
union cvmx_pow_wq_int_pc int_pc;
|
|
|
|
for (i = 0; i < TOTAL_NUMBER_OF_PORTS; i++) {
|
|
if (cvm_oct_device[i]) {
|
|
dev_for_napi = cvm_oct_device[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (NULL == dev_for_napi)
|
|
panic("No net_devices were allocated.");
|
|
|
|
if (max_rx_cpus > 1 && max_rx_cpus < num_online_cpus())
|
|
atomic_set(&core_state.available_cores, max_rx_cpus);
|
|
else
|
|
atomic_set(&core_state.available_cores, num_online_cpus());
|
|
core_state.baseline_cores = atomic_read(&core_state.available_cores);
|
|
|
|
core_state.cpu_state = CPU_MASK_NONE;
|
|
for_each_possible_cpu(i) {
|
|
netif_napi_add(dev_for_napi, &cvm_oct_napi[i].napi,
|
|
cvm_oct_napi_poll, rx_napi_weight);
|
|
napi_enable(&cvm_oct_napi[i].napi);
|
|
}
|
|
/* Register an IRQ hander for to receive POW interrupts */
|
|
i = request_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group,
|
|
cvm_oct_do_interrupt, 0, "Ethernet", cvm_oct_device);
|
|
|
|
if (i)
|
|
panic("Could not acquire Ethernet IRQ %d\n",
|
|
OCTEON_IRQ_WORKQ0 + pow_receive_group);
|
|
|
|
disable_irq_nosync(OCTEON_IRQ_WORKQ0 + pow_receive_group);
|
|
|
|
int_thr.u64 = 0;
|
|
int_thr.s.tc_en = 1;
|
|
int_thr.s.tc_thr = 1;
|
|
/* Enable POW interrupt when our port has at least one packet */
|
|
cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), int_thr.u64);
|
|
|
|
int_pc.u64 = 0;
|
|
int_pc.s.pc_thr = 5;
|
|
cvmx_write_csr(CVMX_POW_WQ_INT_PC, int_pc.u64);
|
|
|
|
|
|
/* Scheduld NAPI now. This will indirectly enable interrupts. */
|
|
cvm_oct_enable_one_cpu();
|
|
}
|
|
|
|
void cvm_oct_rx_shutdown(void)
|
|
{
|
|
int i;
|
|
/* Shutdown all of the NAPIs */
|
|
for_each_possible_cpu(i)
|
|
netif_napi_del(&cvm_oct_napi[i].napi);
|
|
}
|