016002312d
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
387 lines
12 KiB
C
387 lines
12 KiB
C
#ifndef BCM43xx_DMA_H_
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#define BCM43xx_DMA_H_
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/dma-mapping.h>
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#include <linux/linkage.h>
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#include <asm/atomic.h>
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/* DMA-Interrupt reasons. */
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#define BCM43xx_DMAIRQ_FATALMASK ((1 << 10) | (1 << 11) | (1 << 12) \
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| (1 << 14) | (1 << 15))
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#define BCM43xx_DMAIRQ_NONFATALMASK (1 << 13)
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#define BCM43xx_DMAIRQ_RX_DONE (1 << 16)
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/*** 32-bit DMA Engine. ***/
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/* 32-bit DMA controller registers. */
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#define BCM43xx_DMA32_TXCTL 0x00
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#define BCM43xx_DMA32_TXENABLE 0x00000001
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#define BCM43xx_DMA32_TXSUSPEND 0x00000002
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#define BCM43xx_DMA32_TXLOOPBACK 0x00000004
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#define BCM43xx_DMA32_TXFLUSH 0x00000010
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#define BCM43xx_DMA32_TXADDREXT_MASK 0x00030000
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#define BCM43xx_DMA32_TXADDREXT_SHIFT 16
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#define BCM43xx_DMA32_TXRING 0x04
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#define BCM43xx_DMA32_TXINDEX 0x08
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#define BCM43xx_DMA32_TXSTATUS 0x0C
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#define BCM43xx_DMA32_TXDPTR 0x00000FFF
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#define BCM43xx_DMA32_TXSTATE 0x0000F000
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#define BCM43xx_DMA32_TXSTAT_DISABLED 0x00000000
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#define BCM43xx_DMA32_TXSTAT_ACTIVE 0x00001000
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#define BCM43xx_DMA32_TXSTAT_IDLEWAIT 0x00002000
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#define BCM43xx_DMA32_TXSTAT_STOPPED 0x00003000
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#define BCM43xx_DMA32_TXSTAT_SUSP 0x00004000
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#define BCM43xx_DMA32_TXERROR 0x000F0000
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#define BCM43xx_DMA32_TXERR_NOERR 0x00000000
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#define BCM43xx_DMA32_TXERR_PROT 0x00010000
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#define BCM43xx_DMA32_TXERR_UNDERRUN 0x00020000
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#define BCM43xx_DMA32_TXERR_BUFREAD 0x00030000
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#define BCM43xx_DMA32_TXERR_DESCREAD 0x00040000
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#define BCM43xx_DMA32_TXACTIVE 0xFFF00000
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#define BCM43xx_DMA32_RXCTL 0x10
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#define BCM43xx_DMA32_RXENABLE 0x00000001
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#define BCM43xx_DMA32_RXFROFF_MASK 0x000000FE
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#define BCM43xx_DMA32_RXFROFF_SHIFT 1
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#define BCM43xx_DMA32_RXDIRECTFIFO 0x00000100
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#define BCM43xx_DMA32_RXADDREXT_MASK 0x00030000
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#define BCM43xx_DMA32_RXADDREXT_SHIFT 16
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#define BCM43xx_DMA32_RXRING 0x14
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#define BCM43xx_DMA32_RXINDEX 0x18
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#define BCM43xx_DMA32_RXSTATUS 0x1C
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#define BCM43xx_DMA32_RXDPTR 0x00000FFF
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#define BCM43xx_DMA32_RXSTATE 0x0000F000
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#define BCM43xx_DMA32_RXSTAT_DISABLED 0x00000000
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#define BCM43xx_DMA32_RXSTAT_ACTIVE 0x00001000
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#define BCM43xx_DMA32_RXSTAT_IDLEWAIT 0x00002000
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#define BCM43xx_DMA32_RXSTAT_STOPPED 0x00003000
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#define BCM43xx_DMA32_RXERROR 0x000F0000
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#define BCM43xx_DMA32_RXERR_NOERR 0x00000000
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#define BCM43xx_DMA32_RXERR_PROT 0x00010000
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#define BCM43xx_DMA32_RXERR_OVERFLOW 0x00020000
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#define BCM43xx_DMA32_RXERR_BUFWRITE 0x00030000
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#define BCM43xx_DMA32_RXERR_DESCREAD 0x00040000
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#define BCM43xx_DMA32_RXACTIVE 0xFFF00000
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/* 32-bit DMA descriptor. */
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struct bcm43xx_dmadesc32 {
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__le32 control;
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__le32 address;
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} __attribute__((__packed__));
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#define BCM43xx_DMA32_DCTL_BYTECNT 0x00001FFF
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#define BCM43xx_DMA32_DCTL_ADDREXT_MASK 0x00030000
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#define BCM43xx_DMA32_DCTL_ADDREXT_SHIFT 16
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#define BCM43xx_DMA32_DCTL_DTABLEEND 0x10000000
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#define BCM43xx_DMA32_DCTL_IRQ 0x20000000
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#define BCM43xx_DMA32_DCTL_FRAMEEND 0x40000000
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#define BCM43xx_DMA32_DCTL_FRAMESTART 0x80000000
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/* Address field Routing value. */
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#define BCM43xx_DMA32_ROUTING 0xC0000000
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#define BCM43xx_DMA32_ROUTING_SHIFT 30
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#define BCM43xx_DMA32_NOTRANS 0x00000000
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#define BCM43xx_DMA32_CLIENTTRANS 0x40000000
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/*** 64-bit DMA Engine. ***/
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/* 64-bit DMA controller registers. */
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#define BCM43xx_DMA64_TXCTL 0x00
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#define BCM43xx_DMA64_TXENABLE 0x00000001
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#define BCM43xx_DMA64_TXSUSPEND 0x00000002
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#define BCM43xx_DMA64_TXLOOPBACK 0x00000004
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#define BCM43xx_DMA64_TXFLUSH 0x00000010
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#define BCM43xx_DMA64_TXADDREXT_MASK 0x00030000
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#define BCM43xx_DMA64_TXADDREXT_SHIFT 16
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#define BCM43xx_DMA64_TXINDEX 0x04
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#define BCM43xx_DMA64_TXRINGLO 0x08
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#define BCM43xx_DMA64_TXRINGHI 0x0C
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#define BCM43xx_DMA64_TXSTATUS 0x10
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#define BCM43xx_DMA64_TXSTATDPTR 0x00001FFF
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#define BCM43xx_DMA64_TXSTAT 0xF0000000
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#define BCM43xx_DMA64_TXSTAT_DISABLED 0x00000000
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#define BCM43xx_DMA64_TXSTAT_ACTIVE 0x10000000
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#define BCM43xx_DMA64_TXSTAT_IDLEWAIT 0x20000000
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#define BCM43xx_DMA64_TXSTAT_STOPPED 0x30000000
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#define BCM43xx_DMA64_TXSTAT_SUSP 0x40000000
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#define BCM43xx_DMA64_TXERROR 0x14
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#define BCM43xx_DMA64_TXERRDPTR 0x0001FFFF
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#define BCM43xx_DMA64_TXERR 0xF0000000
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#define BCM43xx_DMA64_TXERR_NOERR 0x00000000
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#define BCM43xx_DMA64_TXERR_PROT 0x10000000
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#define BCM43xx_DMA64_TXERR_UNDERRUN 0x20000000
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#define BCM43xx_DMA64_TXERR_TRANSFER 0x30000000
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#define BCM43xx_DMA64_TXERR_DESCREAD 0x40000000
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#define BCM43xx_DMA64_TXERR_CORE 0x50000000
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#define BCM43xx_DMA64_RXCTL 0x20
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#define BCM43xx_DMA64_RXENABLE 0x00000001
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#define BCM43xx_DMA64_RXFROFF_MASK 0x000000FE
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#define BCM43xx_DMA64_RXFROFF_SHIFT 1
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#define BCM43xx_DMA64_RXDIRECTFIFO 0x00000100
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#define BCM43xx_DMA64_RXADDREXT_MASK 0x00030000
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#define BCM43xx_DMA64_RXADDREXT_SHIFT 16
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#define BCM43xx_DMA64_RXINDEX 0x24
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#define BCM43xx_DMA64_RXRINGLO 0x28
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#define BCM43xx_DMA64_RXRINGHI 0x2C
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#define BCM43xx_DMA64_RXSTATUS 0x30
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#define BCM43xx_DMA64_RXSTATDPTR 0x00001FFF
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#define BCM43xx_DMA64_RXSTAT 0xF0000000
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#define BCM43xx_DMA64_RXSTAT_DISABLED 0x00000000
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#define BCM43xx_DMA64_RXSTAT_ACTIVE 0x10000000
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#define BCM43xx_DMA64_RXSTAT_IDLEWAIT 0x20000000
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#define BCM43xx_DMA64_RXSTAT_STOPPED 0x30000000
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#define BCM43xx_DMA64_RXSTAT_SUSP 0x40000000
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#define BCM43xx_DMA64_RXERROR 0x34
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#define BCM43xx_DMA64_RXERRDPTR 0x0001FFFF
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#define BCM43xx_DMA64_RXERR 0xF0000000
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#define BCM43xx_DMA64_RXERR_NOERR 0x00000000
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#define BCM43xx_DMA64_RXERR_PROT 0x10000000
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#define BCM43xx_DMA64_RXERR_UNDERRUN 0x20000000
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#define BCM43xx_DMA64_RXERR_TRANSFER 0x30000000
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#define BCM43xx_DMA64_RXERR_DESCREAD 0x40000000
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#define BCM43xx_DMA64_RXERR_CORE 0x50000000
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/* 64-bit DMA descriptor. */
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struct bcm43xx_dmadesc64 {
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__le32 control0;
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__le32 control1;
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__le32 address_low;
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__le32 address_high;
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} __attribute__((__packed__));
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#define BCM43xx_DMA64_DCTL0_DTABLEEND 0x10000000
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#define BCM43xx_DMA64_DCTL0_IRQ 0x20000000
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#define BCM43xx_DMA64_DCTL0_FRAMEEND 0x40000000
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#define BCM43xx_DMA64_DCTL0_FRAMESTART 0x80000000
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#define BCM43xx_DMA64_DCTL1_BYTECNT 0x00001FFF
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#define BCM43xx_DMA64_DCTL1_ADDREXT_MASK 0x00030000
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#define BCM43xx_DMA64_DCTL1_ADDREXT_SHIFT 16
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/* Address field Routing value. */
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#define BCM43xx_DMA64_ROUTING 0xC0000000
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#define BCM43xx_DMA64_ROUTING_SHIFT 30
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#define BCM43xx_DMA64_NOTRANS 0x00000000
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#define BCM43xx_DMA64_CLIENTTRANS 0x80000000
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struct bcm43xx_dmadesc_generic {
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union {
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struct bcm43xx_dmadesc32 dma32;
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struct bcm43xx_dmadesc64 dma64;
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} __attribute__((__packed__));
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} __attribute__((__packed__));
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/* Misc DMA constants */
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#define BCM43xx_DMA_RINGMEMSIZE PAGE_SIZE
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#define BCM43xx_DMA0_RX_FRAMEOFFSET 30
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#define BCM43xx_DMA3_RX_FRAMEOFFSET 0
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/* DMA engine tuning knobs */
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#define BCM43xx_TXRING_SLOTS 512
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#define BCM43xx_RXRING_SLOTS 64
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#define BCM43xx_DMA0_RX_BUFFERSIZE (2304 + 100)
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#define BCM43xx_DMA3_RX_BUFFERSIZE 16
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/* Suspend the tx queue, if less than this percent slots are free. */
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#define BCM43xx_TXSUSPEND_PERCENT 20
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/* Resume the tx queue, if more than this percent slots are free. */
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#define BCM43xx_TXRESUME_PERCENT 50
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#ifdef CONFIG_BCM43XX_DMA
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struct sk_buff;
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struct bcm43xx_private;
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struct bcm43xx_xmitstatus;
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struct bcm43xx_dmadesc_meta {
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/* The kernel DMA-able buffer. */
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struct sk_buff *skb;
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/* DMA base bus-address of the descriptor buffer. */
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dma_addr_t dmaaddr;
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};
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struct bcm43xx_dmaring {
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/* Kernel virtual base address of the ring memory. */
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void *descbase;
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/* Meta data about all descriptors. */
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struct bcm43xx_dmadesc_meta *meta;
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/* DMA Routing value. */
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u32 routing;
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/* (Unadjusted) DMA base bus-address of the ring memory. */
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dma_addr_t dmabase;
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/* Number of descriptor slots in the ring. */
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int nr_slots;
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/* Number of used descriptor slots. */
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int used_slots;
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/* Currently used slot in the ring. */
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int current_slot;
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/* Marks to suspend/resume the queue. */
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int suspend_mark;
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int resume_mark;
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/* Frameoffset in octets. */
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u32 frameoffset;
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/* Descriptor buffer size. */
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u16 rx_buffersize;
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/* The MMIO base register of the DMA controller. */
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u16 mmio_base;
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/* DMA controller index number (0-5). */
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int index;
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/* Boolean. Is this a TX ring? */
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u8 tx;
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/* Boolean. 64bit DMA if true, 32bit DMA otherwise. */
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u8 dma64;
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/* Boolean. Are transfers suspended on this ring? */
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u8 suspended;
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struct bcm43xx_private *bcm;
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#ifdef CONFIG_BCM43XX_DEBUG
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/* Maximum number of used slots. */
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int max_used_slots;
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#endif /* CONFIG_BCM43XX_DEBUG*/
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};
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static inline
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int bcm43xx_dma_desc2idx(struct bcm43xx_dmaring *ring,
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struct bcm43xx_dmadesc_generic *desc)
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{
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if (ring->dma64) {
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struct bcm43xx_dmadesc64 *dd64 = ring->descbase;
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return (int)(&(desc->dma64) - dd64);
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} else {
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struct bcm43xx_dmadesc32 *dd32 = ring->descbase;
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return (int)(&(desc->dma32) - dd32);
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}
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}
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static inline
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struct bcm43xx_dmadesc_generic * bcm43xx_dma_idx2desc(struct bcm43xx_dmaring *ring,
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int slot,
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struct bcm43xx_dmadesc_meta **meta)
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{
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*meta = &(ring->meta[slot]);
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if (ring->dma64) {
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struct bcm43xx_dmadesc64 *dd64 = ring->descbase;
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return (struct bcm43xx_dmadesc_generic *)(&(dd64[slot]));
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} else {
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struct bcm43xx_dmadesc32 *dd32 = ring->descbase;
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return (struct bcm43xx_dmadesc_generic *)(&(dd32[slot]));
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}
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}
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static inline
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u32 bcm43xx_dma_read(struct bcm43xx_dmaring *ring,
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u16 offset)
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{
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return bcm43xx_read32(ring->bcm, ring->mmio_base + offset);
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}
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static inline
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void bcm43xx_dma_write(struct bcm43xx_dmaring *ring,
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u16 offset, u32 value)
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{
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bcm43xx_write32(ring->bcm, ring->mmio_base + offset, value);
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}
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int bcm43xx_dma_init(struct bcm43xx_private *bcm);
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void bcm43xx_dma_free(struct bcm43xx_private *bcm);
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int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
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u16 dmacontroller_mmio_base,
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int dma64);
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int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
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u16 dmacontroller_mmio_base,
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int dma64);
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u16 bcm43xx_dmacontroller_base(int dma64bit, int dmacontroller_idx);
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void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring);
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void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring);
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void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
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struct bcm43xx_xmitstatus *status);
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int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
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struct ieee80211_txb *txb);
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void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring);
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/* Helper function that returns the dma mask for this device. */
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static inline
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u64 bcm43xx_get_supported_dma_mask(struct bcm43xx_private *bcm)
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{
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int dma64 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH) &
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BCM43xx_SBTMSTATEHIGH_DMA64BIT;
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u16 mmio_base = bcm43xx_dmacontroller_base(dma64, 0);
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u32 mask = BCM43xx_DMA32_TXADDREXT_MASK;
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if (dma64)
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return DMA_64BIT_MASK;
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bcm43xx_write32(bcm, mmio_base + BCM43xx_DMA32_TXCTL, mask);
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if (bcm43xx_read32(bcm, mmio_base + BCM43xx_DMA32_TXCTL) & mask)
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return DMA_32BIT_MASK;
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return DMA_30BIT_MASK;
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}
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#else /* CONFIG_BCM43XX_DMA */
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static inline
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int bcm43xx_dma_init(struct bcm43xx_private *bcm)
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{
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return 0;
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}
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static inline
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void bcm43xx_dma_free(struct bcm43xx_private *bcm)
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{
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}
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static inline
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int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
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u16 dmacontroller_mmio_base,
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int dma64)
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{
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return 0;
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}
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static inline
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int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
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u16 dmacontroller_mmio_base,
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int dma64)
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{
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return 0;
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}
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static inline
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int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
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struct ieee80211_txb *txb)
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{
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return 0;
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}
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static inline
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void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
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struct bcm43xx_xmitstatus *status)
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{
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}
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static inline
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void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
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{
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}
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static inline
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void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring)
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{
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}
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static inline
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void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring)
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{
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}
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#endif /* CONFIG_BCM43XX_DMA */
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#endif /* BCM43xx_DMA_H_ */
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