d766a4eda6
Currently SMC911x driver is broken on ARM/PXA builds. Unbreak such configurations. Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
912 lines
32 KiB
C
912 lines
32 KiB
C
/*------------------------------------------------------------------------
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. smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
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.
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. Copyright (C) 2005 Sensoria Corp.
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. Derived from the unified SMC91x driver by Nicolas Pitre
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.
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. This program is free software; you can redistribute it and/or modify
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. it under the terms of the GNU General Public License as published by
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. the Free Software Foundation; either version 2 of the License, or
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. (at your option) any later version.
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.
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. This program is distributed in the hope that it will be useful,
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. but WITHOUT ANY WARRANTY; without even the implied warranty of
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. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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. GNU General Public License for more details.
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.
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. You should have received a copy of the GNU General Public License
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. along with this program; if not, write to the Free Software
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. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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.
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. Information contained in this file was obtained from the LAN9118
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. manual from SMC. To get a copy, if you really want one, you can find
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. information under www.smsc.com.
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.
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. Authors
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. Dustin McIntire <dustin@sensoria.com>
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.
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---------------------------------------------------------------------------*/
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#ifndef _SMC911X_H_
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#define _SMC911X_H_
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#include <linux/smc911x.h>
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/*
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* Use the DMA feature on PXA chips
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*/
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#ifdef CONFIG_ARCH_PXA
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#define SMC_USE_PXA_DMA 1
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#define SMC_USE_16BIT 0
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#define SMC_USE_32BIT 1
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#define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
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#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
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#define SMC_USE_16BIT 0
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#define SMC_USE_32BIT 1
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#define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
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#else
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/*
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* Default configuration
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*/
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#define SMC_DYNAMIC_BUS_CONFIG
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#endif
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#ifdef SMC_USE_PXA_DMA
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#define SMC_USE_DMA
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#endif
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/* store this information for the driver.. */
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struct smc911x_local {
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/*
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* If I have to wait until the DMA is finished and ready to reload a
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* packet, I will store the skbuff here. Then, the DMA will send it
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* out and free it.
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*/
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struct sk_buff *pending_tx_skb;
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/* version/revision of the SMC911x chip */
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u16 version;
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u16 revision;
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/* FIFO sizes */
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int tx_fifo_kb;
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int tx_fifo_size;
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int rx_fifo_size;
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int afc_cfg;
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/* Contains the current active receive/phy mode */
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int ctl_rfduplx;
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int ctl_rspeed;
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u32 msg_enable;
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u32 phy_type;
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struct mii_if_info mii;
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/* work queue */
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struct work_struct phy_configure;
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int tx_throttle;
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spinlock_t lock;
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struct net_device *netdev;
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#ifdef SMC_USE_DMA
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/* DMA needs the physical address of the chip */
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u_long physaddr;
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int rxdma;
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int txdma;
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int rxdma_active;
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int txdma_active;
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struct sk_buff *current_rx_skb;
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struct sk_buff *current_tx_skb;
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struct device *dev;
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#endif
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void __iomem *base;
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#ifdef SMC_DYNAMIC_BUS_CONFIG
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struct smc911x_platdata cfg;
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#endif
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};
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/*
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* Define the bus width specific IO macros
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*/
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#ifdef SMC_DYNAMIC_BUS_CONFIG
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static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
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{
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void __iomem *ioaddr = lp->base + reg;
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if (lp->cfg.flags & SMC911X_USE_32BIT)
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return readl(ioaddr);
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if (lp->cfg.flags & SMC911X_USE_16BIT)
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return readw(ioaddr) | (readw(ioaddr + 2) << 16);
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BUG();
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}
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static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
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int reg)
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{
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void __iomem *ioaddr = lp->base + reg;
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if (lp->cfg.flags & SMC911X_USE_32BIT) {
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writel(value, ioaddr);
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return;
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}
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if (lp->cfg.flags & SMC911X_USE_16BIT) {
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writew(value & 0xffff, ioaddr);
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writew(value >> 16, ioaddr + 2);
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return;
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}
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BUG();
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}
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static inline void SMC_insl(struct smc911x_local *lp, int reg,
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void *addr, unsigned int count)
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{
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void __iomem *ioaddr = lp->base + reg;
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if (lp->cfg.flags & SMC911X_USE_32BIT) {
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readsl(ioaddr, addr, count);
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return;
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}
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if (lp->cfg.flags & SMC911X_USE_16BIT) {
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readsw(ioaddr, addr, count * 2);
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return;
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}
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BUG();
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}
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static inline void SMC_outsl(struct smc911x_local *lp, int reg,
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void *addr, unsigned int count)
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{
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void __iomem *ioaddr = lp->base + reg;
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if (lp->cfg.flags & SMC911X_USE_32BIT) {
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writesl(ioaddr, addr, count);
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return;
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}
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if (lp->cfg.flags & SMC911X_USE_16BIT) {
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writesw(ioaddr, addr, count * 2);
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return;
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}
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BUG();
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}
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#else
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#if SMC_USE_16BIT
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#define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
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#define SMC_outl(v, lp, r) \
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do{ \
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writew(v & 0xFFFF, (lp)->base + (r)); \
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writew(v >> 16, (lp)->base + (r) + 2); \
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} while (0)
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#define SMC_insl(lp, r, p, l) readsw((short*)((lp)->base + (r)), p, l*2)
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#define SMC_outsl(lp, r, p, l) writesw((short*)((lp)->base + (r)), p, l*2)
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#elif SMC_USE_32BIT
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#define SMC_inl(lp, r) readl((lp)->base + (r))
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#define SMC_outl(v, lp, r) writel(v, (lp)->base + (r))
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#define SMC_insl(lp, r, p, l) readsl((int*)((lp)->base + (r)), p, l)
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#define SMC_outsl(lp, r, p, l) writesl((int*)((lp)->base + (r)), p, l)
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#endif /* SMC_USE_16BIT */
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#endif /* SMC_DYNAMIC_BUS_CONFIG */
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#ifdef SMC_USE_PXA_DMA
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/*
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* Define the request and free functions
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* These are unfortunately architecture specific as no generic allocation
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* mechanism exits
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*/
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#define SMC_DMA_REQUEST(dev, handler) \
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pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
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#define SMC_DMA_FREE(dev, dma) \
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pxa_free_dma(dma)
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#define SMC_DMA_ACK_IRQ(dev, dma) \
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{ \
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if (DCSR(dma) & DCSR_BUSERR) { \
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printk("%s: DMA %d bus error!\n", dev->name, dma); \
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} \
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DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; \
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}
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/*
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* Use a DMA for RX and TX packets.
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*/
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#include <linux/dma-mapping.h>
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#include <asm/dma.h>
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#include <mach/pxa-regs.h>
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static dma_addr_t rx_dmabuf, tx_dmabuf;
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static int rx_dmalen, tx_dmalen;
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#ifdef SMC_insl
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#undef SMC_insl
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#define SMC_insl(lp, r, p, l) \
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smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
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static inline void
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smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
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int reg, int dma, u_char *buf, int len)
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{
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/* 64 bit alignment is required for memory to memory DMA */
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if ((long)buf & 4) {
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*((u32 *)buf) = SMC_inl(lp, reg);
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buf += 4;
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len--;
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}
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len *= 4;
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rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
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rx_dmalen = len;
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DCSR(dma) = DCSR_NODESC;
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DTADR(dma) = rx_dmabuf;
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DSADR(dma) = physaddr + reg;
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DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
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DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
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DCSR(dma) = DCSR_NODESC | DCSR_RUN;
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}
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#endif
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#ifdef SMC_outsl
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#undef SMC_outsl
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#define SMC_outsl(lp, r, p, l) \
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smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
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static inline void
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smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
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int reg, int dma, u_char *buf, int len)
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{
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/* 64 bit alignment is required for memory to memory DMA */
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if ((long)buf & 4) {
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SMC_outl(*((u32 *)buf), lp, reg);
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buf += 4;
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len--;
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}
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len *= 4;
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tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
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tx_dmalen = len;
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DCSR(dma) = DCSR_NODESC;
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DSADR(dma) = tx_dmabuf;
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DTADR(dma) = physaddr + reg;
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DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
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DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
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DCSR(dma) = DCSR_NODESC | DCSR_RUN;
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}
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#endif
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#endif /* SMC_USE_PXA_DMA */
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/* Chip Parameters and Register Definitions */
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#define SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2)
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#define SMC911X_IO_EXTENT 0x100
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#define SMC911X_EEPROM_LEN 7
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/* Below are the register offsets and bit definitions
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* of the Lan911x memory space
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*/
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#define RX_DATA_FIFO (0x00)
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#define TX_DATA_FIFO (0x20)
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#define TX_CMD_A_INT_ON_COMP_ (0x80000000)
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#define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000)
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#define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000)
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#define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000)
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#define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000)
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#define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000)
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#define TX_CMD_A_INT_FIRST_SEG_ (0x00002000)
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#define TX_CMD_A_INT_LAST_SEG_ (0x00001000)
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#define TX_CMD_A_BUF_SIZE_ (0x000007FF)
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#define TX_CMD_B_PKT_TAG_ (0xFFFF0000)
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#define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000)
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#define TX_CMD_B_DISABLE_PADDING_ (0x00001000)
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#define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF)
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#define RX_STATUS_FIFO (0x40)
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#define RX_STS_PKT_LEN_ (0x3FFF0000)
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#define RX_STS_ES_ (0x00008000)
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#define RX_STS_BCST_ (0x00002000)
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#define RX_STS_LEN_ERR_ (0x00001000)
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#define RX_STS_RUNT_ERR_ (0x00000800)
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#define RX_STS_MCAST_ (0x00000400)
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#define RX_STS_TOO_LONG_ (0x00000080)
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#define RX_STS_COLL_ (0x00000040)
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#define RX_STS_ETH_TYPE_ (0x00000020)
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#define RX_STS_WDOG_TMT_ (0x00000010)
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#define RX_STS_MII_ERR_ (0x00000008)
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#define RX_STS_DRIBBLING_ (0x00000004)
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#define RX_STS_CRC_ERR_ (0x00000002)
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#define RX_STATUS_FIFO_PEEK (0x44)
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#define TX_STATUS_FIFO (0x48)
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#define TX_STS_TAG_ (0xFFFF0000)
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#define TX_STS_ES_ (0x00008000)
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#define TX_STS_LOC_ (0x00000800)
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#define TX_STS_NO_CARR_ (0x00000400)
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#define TX_STS_LATE_COLL_ (0x00000200)
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#define TX_STS_MANY_COLL_ (0x00000100)
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#define TX_STS_COLL_CNT_ (0x00000078)
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#define TX_STS_MANY_DEFER_ (0x00000004)
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#define TX_STS_UNDERRUN_ (0x00000002)
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#define TX_STS_DEFERRED_ (0x00000001)
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#define TX_STATUS_FIFO_PEEK (0x4C)
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#define ID_REV (0x50)
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#define ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */
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#define ID_REV_REV_ID_ (0x0000FFFF) /* RO */
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#define INT_CFG (0x54)
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#define INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */
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#define INT_CFG_INT_DEAS_CLR_ (0x00004000)
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#define INT_CFG_INT_DEAS_STS_ (0x00002000)
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#define INT_CFG_IRQ_INT_ (0x00001000) /* RO */
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#define INT_CFG_IRQ_EN_ (0x00000100) /* R/W */
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#define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */
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#define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */
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#define INT_STS (0x58)
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#define INT_STS_SW_INT_ (0x80000000) /* R/WC */
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#define INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */
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#define INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */
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#define INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */
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#define INT_STS_RXDF_INT_ (0x00400000) /* R/WC */
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#define INT_STS_TX_IOC_ (0x00200000) /* R/WC */
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#define INT_STS_RXD_INT_ (0x00100000) /* R/WC */
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#define INT_STS_GPT_INT_ (0x00080000) /* R/WC */
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#define INT_STS_PHY_INT_ (0x00040000) /* RO */
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#define INT_STS_PME_INT_ (0x00020000) /* R/WC */
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#define INT_STS_TXSO_ (0x00010000) /* R/WC */
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#define INT_STS_RWT_ (0x00008000) /* R/WC */
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#define INT_STS_RXE_ (0x00004000) /* R/WC */
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#define INT_STS_TXE_ (0x00002000) /* R/WC */
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//#define INT_STS_ERX_ (0x00001000) /* R/WC */
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#define INT_STS_TDFU_ (0x00000800) /* R/WC */
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#define INT_STS_TDFO_ (0x00000400) /* R/WC */
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#define INT_STS_TDFA_ (0x00000200) /* R/WC */
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#define INT_STS_TSFF_ (0x00000100) /* R/WC */
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#define INT_STS_TSFL_ (0x00000080) /* R/WC */
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//#define INT_STS_RXDF_ (0x00000040) /* R/WC */
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#define INT_STS_RDFO_ (0x00000040) /* R/WC */
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#define INT_STS_RDFL_ (0x00000020) /* R/WC */
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#define INT_STS_RSFF_ (0x00000010) /* R/WC */
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#define INT_STS_RSFL_ (0x00000008) /* R/WC */
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#define INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */
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#define INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */
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#define INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */
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#define INT_EN (0x5C)
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#define INT_EN_SW_INT_EN_ (0x80000000) /* R/W */
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#define INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */
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#define INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */
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#define INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */
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//#define INT_EN_RXDF_INT_EN_ (0x00400000) /* R/W */
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#define INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */
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#define INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */
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#define INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */
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#define INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */
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#define INT_EN_PME_INT_EN_ (0x00020000) /* R/W */
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#define INT_EN_TXSO_EN_ (0x00010000) /* R/W */
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#define INT_EN_RWT_EN_ (0x00008000) /* R/W */
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#define INT_EN_RXE_EN_ (0x00004000) /* R/W */
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#define INT_EN_TXE_EN_ (0x00002000) /* R/W */
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//#define INT_EN_ERX_EN_ (0x00001000) /* R/W */
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#define INT_EN_TDFU_EN_ (0x00000800) /* R/W */
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#define INT_EN_TDFO_EN_ (0x00000400) /* R/W */
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#define INT_EN_TDFA_EN_ (0x00000200) /* R/W */
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#define INT_EN_TSFF_EN_ (0x00000100) /* R/W */
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#define INT_EN_TSFL_EN_ (0x00000080) /* R/W */
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//#define INT_EN_RXDF_EN_ (0x00000040) /* R/W */
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#define INT_EN_RDFO_EN_ (0x00000040) /* R/W */
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#define INT_EN_RDFL_EN_ (0x00000020) /* R/W */
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#define INT_EN_RSFF_EN_ (0x00000010) /* R/W */
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#define INT_EN_RSFL_EN_ (0x00000008) /* R/W */
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#define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */
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#define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */
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#define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */
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#define BYTE_TEST (0x64)
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#define FIFO_INT (0x68)
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#define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */
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#define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */
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#define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */
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#define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */
|
|
|
|
#define RX_CFG (0x6C)
|
|
#define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */
|
|
#define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */
|
|
#define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */
|
|
#define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */
|
|
#define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */
|
|
#define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */
|
|
#define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */
|
|
//#define RX_CFG_RXBAD_ (0x00000001) /* R/W */
|
|
|
|
#define TX_CFG (0x70)
|
|
//#define TX_CFG_TX_DMA_LVL_ (0xE0000000) /* R/W */
|
|
//#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000) /* R/W Self Clearing */
|
|
#define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */
|
|
#define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */
|
|
#define TX_CFG_TXSAO_ (0x00000004) /* R/W */
|
|
#define TX_CFG_TX_ON_ (0x00000002) /* R/W */
|
|
#define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */
|
|
|
|
#define HW_CFG (0x74)
|
|
#define HW_CFG_TTM_ (0x00200000) /* R/W */
|
|
#define HW_CFG_SF_ (0x00100000) /* R/W */
|
|
#define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */
|
|
#define HW_CFG_TR_ (0x00003000) /* R/W */
|
|
#define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */
|
|
#define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */
|
|
#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */
|
|
#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */
|
|
#define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */
|
|
#define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */
|
|
#define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */
|
|
#define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */
|
|
#define HW_CFG_SRST_TO_ (0x00000002) /* RO */
|
|
#define HW_CFG_SRST_ (0x00000001) /* Self Clearing */
|
|
|
|
#define RX_DP_CTRL (0x78)
|
|
#define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */
|
|
#define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */
|
|
|
|
#define RX_FIFO_INF (0x7C)
|
|
#define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */
|
|
#define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */
|
|
|
|
#define TX_FIFO_INF (0x80)
|
|
#define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */
|
|
#define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */
|
|
|
|
#define PMT_CTRL (0x84)
|
|
#define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */
|
|
#define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */
|
|
#define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */
|
|
#define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */
|
|
#define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
|
|
#define PMT_CTRL_WUPS_ (0x00000030) /* R/WC */
|
|
#define PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */
|
|
#define PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */
|
|
#define PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */
|
|
#define PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */
|
|
#define PMT_CTRL_PME_IND_ (0x00000008) /* R/W */
|
|
#define PMT_CTRL_PME_POL_ (0x00000004) /* R/W */
|
|
#define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
|
|
#define PMT_CTRL_READY_ (0x00000001) /* RO */
|
|
|
|
#define GPIO_CFG (0x88)
|
|
#define GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */
|
|
#define GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */
|
|
#define GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */
|
|
#define GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */
|
|
#define GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */
|
|
#define GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */
|
|
#define GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */
|
|
#define GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */
|
|
#define GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */
|
|
#define GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */
|
|
#define GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */
|
|
#define GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */
|
|
#define GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */
|
|
#define GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */
|
|
#define GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */
|
|
#define GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */
|
|
#define GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */
|
|
#define GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */
|
|
|
|
#define GPT_CFG (0x8C)
|
|
#define GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */
|
|
#define GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */
|
|
|
|
#define GPT_CNT (0x90)
|
|
#define GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */
|
|
|
|
#define ENDIAN (0x98)
|
|
#define FREE_RUN (0x9C)
|
|
#define RX_DROP (0xA0)
|
|
#define MAC_CSR_CMD (0xA4)
|
|
#define MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */
|
|
#define MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */
|
|
#define MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */
|
|
|
|
#define MAC_CSR_DATA (0xA8)
|
|
#define AFC_CFG (0xAC)
|
|
#define AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */
|
|
#define AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */
|
|
#define AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */
|
|
#define AFC_CFG_FCMULT_ (0x00000008) /* R/W */
|
|
#define AFC_CFG_FCBRD_ (0x00000004) /* R/W */
|
|
#define AFC_CFG_FCADD_ (0x00000002) /* R/W */
|
|
#define AFC_CFG_FCANY_ (0x00000001) /* R/W */
|
|
|
|
#define E2P_CMD (0xB0)
|
|
#define E2P_CMD_EPC_BUSY_ (0x80000000) /* Self Clearing */
|
|
#define E2P_CMD_EPC_CMD_ (0x70000000) /* R/W */
|
|
#define E2P_CMD_EPC_CMD_READ_ (0x00000000) /* R/W */
|
|
#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) /* R/W */
|
|
#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) /* R/W */
|
|
#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) /* R/W */
|
|
#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) /* R/W */
|
|
#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) /* R/W */
|
|
#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) /* R/W */
|
|
#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) /* R/W */
|
|
#define E2P_CMD_EPC_TIMEOUT_ (0x00000200) /* RO */
|
|
#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) /* RO */
|
|
#define E2P_CMD_EPC_ADDR_ (0x000000FF) /* R/W */
|
|
|
|
#define E2P_DATA (0xB4)
|
|
#define E2P_DATA_EEPROM_DATA_ (0x000000FF) /* R/W */
|
|
/* end of LAN register offsets and bit definitions */
|
|
|
|
/*
|
|
****************************************************************************
|
|
****************************************************************************
|
|
* MAC Control and Status Register (Indirect Address)
|
|
* Offset (through the MAC_CSR CMD and DATA port)
|
|
****************************************************************************
|
|
****************************************************************************
|
|
*
|
|
*/
|
|
#define MAC_CR (0x01) /* R/W */
|
|
|
|
/* MAC_CR - MAC Control Register */
|
|
#define MAC_CR_RXALL_ (0x80000000)
|
|
// TODO: delete this bit? It is not described in the data sheet.
|
|
#define MAC_CR_HBDIS_ (0x10000000)
|
|
#define MAC_CR_RCVOWN_ (0x00800000)
|
|
#define MAC_CR_LOOPBK_ (0x00200000)
|
|
#define MAC_CR_FDPX_ (0x00100000)
|
|
#define MAC_CR_MCPAS_ (0x00080000)
|
|
#define MAC_CR_PRMS_ (0x00040000)
|
|
#define MAC_CR_INVFILT_ (0x00020000)
|
|
#define MAC_CR_PASSBAD_ (0x00010000)
|
|
#define MAC_CR_HFILT_ (0x00008000)
|
|
#define MAC_CR_HPFILT_ (0x00002000)
|
|
#define MAC_CR_LCOLL_ (0x00001000)
|
|
#define MAC_CR_BCAST_ (0x00000800)
|
|
#define MAC_CR_DISRTY_ (0x00000400)
|
|
#define MAC_CR_PADSTR_ (0x00000100)
|
|
#define MAC_CR_BOLMT_MASK_ (0x000000C0)
|
|
#define MAC_CR_DFCHK_ (0x00000020)
|
|
#define MAC_CR_TXEN_ (0x00000008)
|
|
#define MAC_CR_RXEN_ (0x00000004)
|
|
|
|
#define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
|
|
#define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
|
|
#define HASHH (0x04) /* R/W */
|
|
#define HASHL (0x05) /* R/W */
|
|
|
|
#define MII_ACC (0x06) /* R/W */
|
|
#define MII_ACC_PHY_ADDR_ (0x0000F800)
|
|
#define MII_ACC_MIIRINDA_ (0x000007C0)
|
|
#define MII_ACC_MII_WRITE_ (0x00000002)
|
|
#define MII_ACC_MII_BUSY_ (0x00000001)
|
|
|
|
#define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
|
|
|
|
#define FLOW (0x08) /* R/W */
|
|
#define FLOW_FCPT_ (0xFFFF0000)
|
|
#define FLOW_FCPASS_ (0x00000004)
|
|
#define FLOW_FCEN_ (0x00000002)
|
|
#define FLOW_FCBSY_ (0x00000001)
|
|
|
|
#define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
|
|
#define VLAN1_VTI1_ (0x0000ffff)
|
|
|
|
#define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
|
|
#define VLAN2_VTI2_ (0x0000ffff)
|
|
|
|
#define WUFF (0x0B) /* WO */
|
|
|
|
#define WUCSR (0x0C) /* R/W */
|
|
#define WUCSR_GUE_ (0x00000200)
|
|
#define WUCSR_WUFR_ (0x00000040)
|
|
#define WUCSR_MPR_ (0x00000020)
|
|
#define WUCSR_WAKE_EN_ (0x00000004)
|
|
#define WUCSR_MPEN_ (0x00000002)
|
|
|
|
/*
|
|
****************************************************************************
|
|
* Chip Specific MII Defines
|
|
****************************************************************************
|
|
*
|
|
* Phy register offsets and bit definitions
|
|
*
|
|
*/
|
|
|
|
#define PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register */
|
|
//#define MODE_CTRL_STS_FASTRIP_ ((u16)0x4000)
|
|
#define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)
|
|
//#define MODE_CTRL_STS_LOWSQEN_ ((u16)0x0800)
|
|
//#define MODE_CTRL_STS_MDPREBP_ ((u16)0x0400)
|
|
//#define MODE_CTRL_STS_FARLOOPBACK_ ((u16)0x0200)
|
|
//#define MODE_CTRL_STS_FASTEST_ ((u16)0x0100)
|
|
//#define MODE_CTRL_STS_REFCLKEN_ ((u16)0x0010)
|
|
//#define MODE_CTRL_STS_PHYADBP_ ((u16)0x0008)
|
|
//#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
|
|
#define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)
|
|
|
|
#define PHY_INT_SRC ((u32)29)
|
|
#define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)
|
|
#define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)
|
|
#define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)
|
|
#define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)
|
|
#define PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008)
|
|
#define PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004)
|
|
#define PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002)
|
|
|
|
#define PHY_INT_MASK ((u32)30)
|
|
#define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)
|
|
#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
|
|
#define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)
|
|
#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
|
|
#define PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008)
|
|
#define PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004)
|
|
#define PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002)
|
|
|
|
#define PHY_SPECIAL ((u32)31)
|
|
#define PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000)
|
|
#define PHY_SPECIAL_RES_ ((u16)0x0040)
|
|
#define PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1)
|
|
#define PHY_SPECIAL_SPD_ ((u16)0x001C)
|
|
#define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)
|
|
#define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)
|
|
#define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)
|
|
#define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)
|
|
|
|
#define LAN911X_INTERNAL_PHY_ID (0x0007C000)
|
|
|
|
/* Chip ID values */
|
|
#define CHIP_9115 0x0115
|
|
#define CHIP_9116 0x0116
|
|
#define CHIP_9117 0x0117
|
|
#define CHIP_9118 0x0118
|
|
#define CHIP_9215 0x115A
|
|
#define CHIP_9217 0x117A
|
|
#define CHIP_9218 0x118A
|
|
|
|
struct chip_id {
|
|
u16 id;
|
|
char *name;
|
|
};
|
|
|
|
static const struct chip_id chip_ids[] = {
|
|
{ CHIP_9115, "LAN9115" },
|
|
{ CHIP_9116, "LAN9116" },
|
|
{ CHIP_9117, "LAN9117" },
|
|
{ CHIP_9118, "LAN9118" },
|
|
{ CHIP_9215, "LAN9215" },
|
|
{ CHIP_9217, "LAN9217" },
|
|
{ CHIP_9218, "LAN9218" },
|
|
{ 0, NULL },
|
|
};
|
|
|
|
#define IS_REV_A(x) ((x & 0xFFFF)==0)
|
|
|
|
/*
|
|
* Macros to abstract register access according to the data bus
|
|
* capabilities. Please use those and not the in/out primitives.
|
|
*/
|
|
/* FIFO read/write macros */
|
|
#define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
|
|
#define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
|
|
#define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO )
|
|
#define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
|
|
|
|
|
|
/* I/O mapped register read/write macros */
|
|
#define SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO )
|
|
#define SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO )
|
|
#define SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK )
|
|
#define SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16)
|
|
#define SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF)
|
|
#define SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG )
|
|
#define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG )
|
|
#define SMC_GET_INT(lp) SMC_inl( lp, INT_STS )
|
|
#define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS )
|
|
#define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
|
|
#define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
|
|
#define SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST )
|
|
#define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST )
|
|
#define SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT )
|
|
#define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT )
|
|
#define SMC_SET_FIFO_TDA(lp, x) \
|
|
do { \
|
|
unsigned long __flags; \
|
|
int __mask; \
|
|
local_irq_save(__flags); \
|
|
__mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24); \
|
|
SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
|
|
local_irq_restore(__flags); \
|
|
} while (0)
|
|
#define SMC_SET_FIFO_TSL(lp, x) \
|
|
do { \
|
|
unsigned long __flags; \
|
|
int __mask; \
|
|
local_irq_save(__flags); \
|
|
__mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16); \
|
|
SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16)); \
|
|
local_irq_restore(__flags); \
|
|
} while (0)
|
|
#define SMC_SET_FIFO_RSA(lp, x) \
|
|
do { \
|
|
unsigned long __flags; \
|
|
int __mask; \
|
|
local_irq_save(__flags); \
|
|
__mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8); \
|
|
SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8)); \
|
|
local_irq_restore(__flags); \
|
|
} while (0)
|
|
#define SMC_SET_FIFO_RSL(lp, x) \
|
|
do { \
|
|
unsigned long __flags; \
|
|
int __mask; \
|
|
local_irq_save(__flags); \
|
|
__mask = SMC_GET_FIFO_INT((lp)) & ~0xFF; \
|
|
SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF)); \
|
|
local_irq_restore(__flags); \
|
|
} while (0)
|
|
#define SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG )
|
|
#define SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG )
|
|
#define SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG )
|
|
#define SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG )
|
|
#define SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG )
|
|
#define SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG )
|
|
#define SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL )
|
|
#define SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL )
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#define SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL )
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#define SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL )
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#define SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG )
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#define SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG )
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#define SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF )
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#define SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF )
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#define SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF )
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#define SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF )
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#define SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG )
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#define SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG )
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#define SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP )
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#define SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP )
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#define SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD )
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#define SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD )
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#define SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA )
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#define SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA )
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#define SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG )
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#define SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG )
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#define SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD )
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#define SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD )
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#define SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA )
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#define SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA )
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/* MAC register read/write macros */
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#define SMC_GET_MAC_CSR(lp,a,v) \
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do { \
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while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
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SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ | \
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MAC_CSR_CMD_R_NOT_W_ | (a) ); \
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while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
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v = SMC_GET_MAC_DATA((lp)); \
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} while (0)
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#define SMC_SET_MAC_CSR(lp,a,v) \
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do { \
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while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
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SMC_SET_MAC_DATA((lp), v); \
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SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
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while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
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} while (0)
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#define SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x )
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#define SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x )
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#define SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x )
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#define SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x )
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#define SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x )
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#define SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x )
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#define SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x )
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#define SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x )
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#define SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x )
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#define SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x )
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#define SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x )
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#define SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x )
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#define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
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#define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
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#define SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x )
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#define SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x )
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#define SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x )
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#define SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x )
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#define SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x )
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#define SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x )
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#define SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x )
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#define SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x )
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#define SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x )
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/* PHY register read/write macros */
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#define SMC_GET_MII(lp,a,phy,v) \
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do { \
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u32 __v; \
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do { \
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SMC_GET_MII_ACC((lp), __v); \
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} while ( __v & MII_ACC_MII_BUSY_ ); \
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SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
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MII_ACC_MII_BUSY_); \
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do { \
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SMC_GET_MII_ACC( (lp), __v); \
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} while ( __v & MII_ACC_MII_BUSY_ ); \
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SMC_GET_MII_DATA((lp), v); \
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} while (0)
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#define SMC_SET_MII(lp,a,phy,v) \
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do { \
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u32 __v; \
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do { \
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SMC_GET_MII_ACC((lp), __v); \
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} while ( __v & MII_ACC_MII_BUSY_ ); \
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SMC_SET_MII_DATA((lp), v); \
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SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
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MII_ACC_MII_BUSY_ | \
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MII_ACC_MII_WRITE_ ); \
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do { \
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SMC_GET_MII_ACC((lp), __v); \
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} while ( __v & MII_ACC_MII_BUSY_ ); \
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} while (0)
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#define SMC_GET_PHY_BMCR(lp,phy,x) SMC_GET_MII( (lp), MII_BMCR, phy, x )
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#define SMC_SET_PHY_BMCR(lp,phy,x) SMC_SET_MII( (lp), MII_BMCR, phy, x )
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#define SMC_GET_PHY_BMSR(lp,phy,x) SMC_GET_MII( (lp), MII_BMSR, phy, x )
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#define SMC_GET_PHY_ID1(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
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#define SMC_GET_PHY_ID2(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
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#define SMC_GET_PHY_MII_ADV(lp,phy,x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
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#define SMC_SET_PHY_MII_ADV(lp,phy,x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
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#define SMC_GET_PHY_MII_LPA(lp,phy,x) SMC_GET_MII( (lp), MII_LPA, phy, x )
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#define SMC_SET_PHY_MII_LPA(lp,phy,x) SMC_SET_MII( (lp), MII_LPA, phy, x )
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#define SMC_GET_PHY_CTRL_STS(lp,phy,x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
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#define SMC_SET_PHY_CTRL_STS(lp,phy,x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
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#define SMC_GET_PHY_INT_SRC(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
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#define SMC_SET_PHY_INT_SRC(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
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#define SMC_GET_PHY_INT_MASK(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
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#define SMC_SET_PHY_INT_MASK(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
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#define SMC_GET_PHY_SPECIAL(lp,phy,x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
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/* Misc read/write macros */
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#ifndef SMC_GET_MAC_ADDR
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#define SMC_GET_MAC_ADDR(lp, addr) \
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do { \
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unsigned int __v; \
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\
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SMC_GET_MAC_CSR((lp), ADDRL, __v); \
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addr[0] = __v; addr[1] = __v >> 8; \
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addr[2] = __v >> 16; addr[3] = __v >> 24; \
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SMC_GET_MAC_CSR((lp), ADDRH, __v); \
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addr[4] = __v; addr[5] = __v >> 8; \
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} while (0)
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#endif
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#define SMC_SET_MAC_ADDR(lp, addr) \
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do { \
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SMC_SET_MAC_CSR((lp), ADDRL, \
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addr[0] | \
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(addr[1] << 8) | \
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(addr[2] << 16) | \
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(addr[3] << 24)); \
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SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
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} while (0)
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#define SMC_WRITE_EEPROM_CMD(lp, cmd, addr) \
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do { \
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while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
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SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a ); \
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while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
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} while (0)
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#endif /* _SMC911X_H_ */
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