64f930361b
UTF-8 for copyright symbols etc included. Typedefs and anything else which would cause actual code changes skipped. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
243 lines
8.5 KiB
C
243 lines
8.5 KiB
C
/*
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* Agere Systems Inc.
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* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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* http://www.agere.com
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*
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*------------------------------------------------------------------------------
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*
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* et1310_tx.h - Defines, structs, enums, prototypes, etc. pertaining to data
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* transmission.
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*
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*------------------------------------------------------------------------------
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*
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* SOFTWARE LICENSE
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*
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* This software is provided subject to the following terms and conditions,
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* which you should read carefully before using the software. Using this
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* software indicates your acceptance of these terms and conditions. If you do
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* not agree with these terms and conditions, do not use the software.
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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*
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* Redistribution and use in source or binary forms, with or without
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* modifications, are permitted provided that the following conditions are met:
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*
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* . Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following Disclaimer as comments in the code as
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* well as in the documentation and/or other materials provided with the
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* distribution.
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*
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* . Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following Disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* . Neither the name of Agere Systems Inc. nor the names of the contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* Disclaimer
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
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* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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*
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*/
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#ifndef __ET1310_TX_H__
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#define __ET1310_TX_H__
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/* Typedefs for Tx Descriptor Ring */
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/*
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* TXDESC_WORD2_t structure holds part of the control bits in the Tx Descriptor
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* ring for the ET-1310
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*/
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typedef union _txdesc_word2_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 vlan_prio:3; /* bits 29-31(VLAN priority) */
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u32 vlan_cfi:1; /* bit 28(cfi) */
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u32 vlan_tag:12; /* bits 16-27(VLAN tag) */
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u32 length_in_bytes:16; /* bits 0-15(packet length) */
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#else
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u32 length_in_bytes:16; /* bits 0-15(packet length) */
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u32 vlan_tag:12; /* bits 16-27(VLAN tag) */
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u32 vlan_cfi:1; /* bit 28(cfi) */
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u32 vlan_prio:3; /* bits 29-31(VLAN priority) */
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#endif /* _BIT_FIELDS_HTOL */
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} bits;
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} TXDESC_WORD2_t, *PTXDESC_WORD2_t;
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/*
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* TXDESC_WORD3_t structure holds part of the control bits in the Tx Descriptor
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* ring for the ET-1310
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*/
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typedef union _txdesc_word3_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 unused:17; /* bits 15-31 */
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u32 udpa:1; /* bit 14(UDP checksum assist) */
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u32 tcpa:1; /* bit 13(TCP checksum assist) */
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u32 ipa:1; /* bit 12(IP checksum assist) */
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u32 vlan:1; /* bit 11(append VLAN tag) */
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u32 hp:1; /* bit 10(Packet is a Huge packet) */
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u32 pp:1; /* bit 9(pad packet) */
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u32 mac:1; /* bit 8(MAC override) */
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u32 crc:1; /* bit 7(append CRC) */
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u32 e:1; /* bit 6(Tx frame has error) */
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u32 pf:1; /* bit 5(send pause frame) */
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u32 bp:1; /* bit 4(Issue half-duplex backpressure (XON/XOFF) */
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u32 cw:1; /* bit 3(Control word - no packet data) */
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u32 ir:1; /* bit 2(interrupt the processor when this pkt sent) */
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u32 f:1; /* bit 1(first packet in the sequence) */
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u32 l:1; /* bit 0(last packet in the sequence) */
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#else
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u32 l:1; /* bit 0(last packet in the sequence) */
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u32 f:1; /* bit 1(first packet in the sequence) */
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u32 ir:1; /* bit 2(interrupt the processor when this pkt sent) */
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u32 cw:1; /* bit 3(Control word - no packet data) */
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u32 bp:1; /* bit 4(Issue half-duplex backpressure (XON/XOFF) */
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u32 pf:1; /* bit 5(send pause frame) */
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u32 e:1; /* bit 6(Tx frame has error) */
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u32 crc:1; /* bit 7(append CRC) */
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u32 mac:1; /* bit 8(MAC override) */
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u32 pp:1; /* bit 9(pad packet) */
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u32 hp:1; /* bit 10(Packet is a Huge packet) */
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u32 vlan:1; /* bit 11(append VLAN tag) */
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u32 ipa:1; /* bit 12(IP checksum assist) */
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u32 tcpa:1; /* bit 13(TCP checksum assist) */
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u32 udpa:1; /* bit 14(UDP checksum assist) */
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u32 unused:17; /* bits 15-31 */
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#endif /* _BIT_FIELDS_HTOL */
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} bits;
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} TXDESC_WORD3_t, *PTXDESC_WORD3_t;
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/* TX_DESC_ENTRY_t is sructure representing each descriptor on the ring */
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typedef struct _tx_desc_entry_t {
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u32 DataBufferPtrHigh;
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u32 DataBufferPtrLow;
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TXDESC_WORD2_t word2; /* control words how to xmit the */
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TXDESC_WORD3_t word3; /* data (detailed above) */
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} TX_DESC_ENTRY_t, *PTX_DESC_ENTRY_t;
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/* Typedefs for Tx DMA engine status writeback */
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/*
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* TX_STATUS_BLOCK_t is sructure representing the status of the Tx DMA engine
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* it sits in free memory, and is pointed to by 0x101c / 0x1020
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*/
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typedef union _tx_status_block_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 unused:21; /* bits 11-31 */
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u32 serv_cpl_wrap:1; /* bit 10 */
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u32 serv_cpl:10; /* bits 0-9 */
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#else
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u32 serv_cpl:10; /* bits 0-9 */
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u32 serv_cpl_wrap:1; /* bit 10 */
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u32 unused:21; /* bits 11-31 */
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#endif
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} bits;
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} TX_STATUS_BLOCK_t, *PTX_STATUS_BLOCK_t;
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/* TCB (Transmit Control Block) */
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typedef struct _MP_TCB {
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struct _MP_TCB *Next;
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u32 Flags;
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u32 Count;
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u32 PacketStaleCount;
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struct sk_buff *Packet;
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u32 PacketLength;
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DMA10W_t WrIndex;
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DMA10W_t WrIndexStart;
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} MP_TCB, *PMP_TCB;
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/* Structure to hold the skb's in a list */
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typedef struct tx_skb_list_elem {
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struct list_head skb_list_elem;
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struct sk_buff *skb;
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} TX_SKB_LIST_ELEM, *PTX_SKB_LIST_ELEM;
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/* TX_RING_t is sructure representing our local reference(s) to the ring */
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typedef struct _tx_ring_t {
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/* TCB (Transmit Control Block) memory and lists */
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PMP_TCB MpTcbMem;
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/* List of TCBs that are ready to be used */
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PMP_TCB TCBReadyQueueHead;
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PMP_TCB TCBReadyQueueTail;
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/* list of TCBs that are currently being sent. NOTE that access to all
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* three of these (including nBusySend) are controlled via the
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* TCBSendQLock. This lock should be secured prior to incementing /
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* decrementing nBusySend, or any queue manipulation on CurrSendHead /
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* Tail
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*/
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PMP_TCB CurrSendHead;
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PMP_TCB CurrSendTail;
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int32_t nBusySend;
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/* List of packets (not TCBs) that were queued for lack of resources */
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struct list_head SendWaitQueue;
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int32_t nWaitSend;
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/* The actual descriptor ring */
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PTX_DESC_ENTRY_t pTxDescRingVa;
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dma_addr_t pTxDescRingPa;
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uint64_t pTxDescRingAdjustedPa;
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uint64_t TxDescOffset;
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/* ReadyToSend indicates where we last wrote to in the descriptor ring. */
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DMA10W_t txDmaReadyToSend;
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/* The location of the write-back status block */
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PTX_STATUS_BLOCK_t pTxStatusVa;
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dma_addr_t pTxStatusPa;
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/* A Block of zeroes used to pad packets that are less than 60 bytes */
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void *pTxDummyBlkVa;
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dma_addr_t pTxDummyBlkPa;
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TXMAC_ERR_t TxMacErr;
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/* Variables to track the Tx interrupt coalescing features */
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int32_t TxPacketsSinceLastinterrupt;
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} TX_RING_t, *PTX_RING_t;
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/* Forward declaration of the frag-list for the following prototypes */
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typedef struct _MP_FRAG_LIST MP_FRAG_LIST, *PMP_FRAG_LIST;
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/* Forward declaration of the private adapter structure */
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struct et131x_adapter;
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/* PROTOTYPES for et1310_tx.c */
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int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter);
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void et131x_tx_dma_memory_free(struct et131x_adapter *adapter);
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void ConfigTxDmaRegs(struct et131x_adapter *pAdapter);
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void et131x_init_send(struct et131x_adapter *adapter);
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void et131x_tx_dma_disable(struct et131x_adapter *pAdapter);
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void et131x_tx_dma_enable(struct et131x_adapter *pAdapter);
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void et131x_handle_send_interrupt(struct et131x_adapter *pAdapter);
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void et131x_free_busy_send_packets(struct et131x_adapter *pAdapter);
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int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev);
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#endif /* __ET1310_TX_H__ */
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