64f930361b
UTF-8 for copyright symbols etc included. Typedefs and anything else which would cause actual code changes skipped. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
219 lines
7.1 KiB
C
219 lines
7.1 KiB
C
/*
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* Agere Systems Inc.
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* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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* http://www.agere.com
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*
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*------------------------------------------------------------------------------
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*
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* et1310_jagcore.c - All code pertaining to the ET1301/ET131x's JAGcore
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*
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*------------------------------------------------------------------------------
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*
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* SOFTWARE LICENSE
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*
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* This software is provided subject to the following terms and conditions,
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* which you should read carefully before using the software. Using this
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* software indicates your acceptance of these terms and conditions. If you do
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* not agree with these terms and conditions, do not use the software.
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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*
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* Redistribution and use in source or binary forms, with or without
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* modifications, are permitted provided that the following conditions are met:
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*
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* . Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following Disclaimer as comments in the code as
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* well as in the documentation and/or other materials provided with the
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* distribution.
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*
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* . Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following Disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* . Neither the name of Agere Systems Inc. nor the names of the contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* Disclaimer
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
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* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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*
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*/
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#include "et131x_version.h"
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#include "et131x_debug.h"
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#include "et131x_defs.h"
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/slab.h>
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#include <linux/ctype.h>
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#include <linux/string.h>
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#include <linux/timer.h>
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#include <linux/interrupt.h>
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#include <linux/in.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <asm/system.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/if_arp.h>
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#include <linux/ioport.h>
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#include "et1310_phy.h"
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#include "et1310_pm.h"
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#include "et1310_jagcore.h"
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#include "et131x_adapter.h"
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#include "et131x_initpci.h"
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/* Data for debugging facilities */
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#ifdef CONFIG_ET131X_DEBUG
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extern dbg_info_t *et131x_dbginfo;
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#endif /* CONFIG_ET131X_DEBUG */
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/**
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* ConfigGlobalRegs - Used to configure the global registers on the JAGCore
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* @pAdpater: pointer to our adapter structure
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*/
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void ConfigGlobalRegs(struct et131x_adapter *pAdapter)
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{
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struct _GLOBAL_t __iomem *pGbl = &pAdapter->CSRAddress->global;
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DBG_ENTER(et131x_dbginfo);
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if (pAdapter->RegistryPhyLoopbk == false) {
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if (pAdapter->RegistryJumboPacket < 2048) {
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/* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
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* block of RAM that the driver can split between Tx
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* and Rx as it desires. Our default is to split it
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* 50/50:
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*/
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writel(0, &pGbl->rxq_start_addr.value);
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writel(pAdapter->RegistryRxMemEnd,
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&pGbl->rxq_end_addr.value);
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writel(pAdapter->RegistryRxMemEnd + 1,
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&pGbl->txq_start_addr.value);
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writel(INTERNAL_MEM_SIZE - 1,
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&pGbl->txq_end_addr.value);
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} else if (pAdapter->RegistryJumboPacket < 8192) {
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/* For jumbo packets > 2k but < 8k, split 50-50. */
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writel(0, &pGbl->rxq_start_addr.value);
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writel(INTERNAL_MEM_RX_OFFSET,
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&pGbl->rxq_end_addr.value);
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writel(INTERNAL_MEM_RX_OFFSET + 1,
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&pGbl->txq_start_addr.value);
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writel(INTERNAL_MEM_SIZE - 1,
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&pGbl->txq_end_addr.value);
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} else {
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/* 9216 is the only packet size greater than 8k that
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* is available. The Tx buffer has to be big enough
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* for one whole packet on the Tx side. We'll make
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* the Tx 9408, and give the rest to Rx
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*/
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writel(0x0000, &pGbl->rxq_start_addr.value);
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writel(0x01b3, &pGbl->rxq_end_addr.value);
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writel(0x01b4, &pGbl->txq_start_addr.value);
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writel(INTERNAL_MEM_SIZE - 1,
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&pGbl->txq_end_addr.value);
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}
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/* Initialize the loopback register. Disable all loopbacks. */
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writel(0, &pGbl->loopback.value);
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} else {
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/* For PHY Line loopback, the memory is configured as if Tx
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* and Rx both have all the memory. This is because the
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* RxMAC will write data into the space, and the TxMAC will
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* read it out.
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*/
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writel(0, &pGbl->rxq_start_addr.value);
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writel(INTERNAL_MEM_SIZE - 1, &pGbl->rxq_end_addr.value);
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writel(0, &pGbl->txq_start_addr.value);
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writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr.value);
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/* Initialize the loopback register (MAC loopback). */
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writel(1, &pGbl->loopback.value);
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}
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/* MSI Register */
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writel(0, &pGbl->msi_config.value);
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/* By default, disable the watchdog timer. It will be enabled when
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* a packet is queued.
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*/
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writel(0, &pGbl->watchdog_timer);
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DBG_LEAVE(et131x_dbginfo);
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}
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/**
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* ConfigMMCRegs - Used to configure the main memory registers in the JAGCore
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* @pAdapter: pointer to our adapter structure
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*/
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void ConfigMMCRegs(struct et131x_adapter *pAdapter)
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{
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MMC_CTRL_t mmc_ctrl = { 0 };
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DBG_ENTER(et131x_dbginfo);
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/* All we need to do is initialize the Memory Control Register */
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mmc_ctrl.bits.force_ce = 0x0;
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mmc_ctrl.bits.rxdma_disable = 0x0;
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mmc_ctrl.bits.txdma_disable = 0x0;
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mmc_ctrl.bits.txmac_disable = 0x0;
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mmc_ctrl.bits.rxmac_disable = 0x0;
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mmc_ctrl.bits.arb_disable = 0x0;
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mmc_ctrl.bits.mmc_enable = 0x1;
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writel(mmc_ctrl.value, &pAdapter->CSRAddress->mmc.mmc_ctrl.value);
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DBG_LEAVE(et131x_dbginfo);
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}
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void et131x_enable_interrupts(struct et131x_adapter *adapter)
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{
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uint32_t MaskValue;
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/* Enable all global interrupts */
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if (adapter->FlowControl == TxOnly || adapter->FlowControl == Both)
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MaskValue = INT_MASK_ENABLE;
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else
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MaskValue = INT_MASK_ENABLE_NO_FLOW;
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if (adapter->DriverNoPhyAccess)
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MaskValue |= 0x10000;
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adapter->CachedMaskValue.value = MaskValue;
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writel(MaskValue, &adapter->CSRAddress->global.int_mask.value);
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}
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void et131x_disable_interrupts(struct et131x_adapter *adapter)
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{
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/* Disable all global interrupts */
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adapter->CachedMaskValue.value = INT_MASK_DISABLE;
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writel(INT_MASK_DISABLE, &adapter->CSRAddress->global.int_mask.value);
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}
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