4a3dcd35c8
1. use GPIO_IRQ_mask[] to select those bits of interest, actually only those "unmasked" GPIO IRQs with their corresponding bits in GPIO_IRQ_mask[] set to "1" should be checked 2. remove #ifdef PXA_LAST_GPIO > 96 .. #endif, GPIO_IRQ_mask[] is used to mask out the irrelevant bits, so that even though the GEDR3 on PXA25x is reserved, it will be masked, and the following code will never run. Another point is that GPIO85- GPIO95 bits within GEDR2 will also be masked out on PXA25x Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
387 lines
7.9 KiB
C
387 lines
7.9 KiB
C
/*
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* linux/arch/arm/mach-pxa/irq.c
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*
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* Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/pxa-regs.h>
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#include "generic.h"
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/*
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* This is for peripheral IRQs internal to the PXA chip.
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*/
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static void pxa_mask_low_irq(unsigned int irq)
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{
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ICMR &= ~(1 << irq);
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}
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static void pxa_unmask_low_irq(unsigned int irq)
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{
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ICMR |= (1 << irq);
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}
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static int pxa_set_wake(unsigned int irq, unsigned int on)
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{
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u32 mask;
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switch (irq) {
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case IRQ_RTCAlrm:
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mask = PWER_RTC;
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break;
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#ifdef CONFIG_PXA27x
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/* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */
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#endif
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default:
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return -EINVAL;
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}
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if (on)
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PWER |= mask;
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else
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PWER &= ~mask;
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return 0;
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}
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static struct irq_chip pxa_internal_chip_low = {
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.name = "SC",
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.ack = pxa_mask_low_irq,
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.mask = pxa_mask_low_irq,
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.unmask = pxa_unmask_low_irq,
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.set_wake = pxa_set_wake,
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};
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void __init pxa_init_irq_low(void)
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{
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int irq;
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/* disable all IRQs */
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ICMR = 0;
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/* all IRQs are IRQ, not FIQ */
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ICLR = 0;
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/* only unmasked interrupts kick us out of idle */
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ICCR = 1;
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for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) {
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set_irq_chip(irq, &pxa_internal_chip_low);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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}
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#ifdef CONFIG_PXA27x
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/*
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* This is for the second set of internal IRQs as found on the PXA27x.
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*/
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static void pxa_mask_high_irq(unsigned int irq)
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{
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ICMR2 &= ~(1 << (irq - 32));
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}
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static void pxa_unmask_high_irq(unsigned int irq)
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{
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ICMR2 |= (1 << (irq - 32));
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}
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static struct irq_chip pxa_internal_chip_high = {
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.name = "SC-hi",
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.ack = pxa_mask_high_irq,
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.mask = pxa_mask_high_irq,
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.unmask = pxa_unmask_high_irq,
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};
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void __init pxa_init_irq_high(void)
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{
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int irq;
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ICMR2 = 0;
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ICLR2 = 0;
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for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) {
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set_irq_chip(irq, &pxa_internal_chip_high);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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}
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#endif
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/* Note that if an input/irq line ever gets changed to an output during
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* suspend, the relevant PWER, PRER, and PFER bits should be cleared.
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*/
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#ifdef CONFIG_PXA27x
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/* PXA27x: Various gpios can issue wakeup events. This logic only
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* handles the simple cases, not the WEMUX2 and WEMUX3 options
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*/
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#define PXA27x_GPIO_NOWAKE_MASK \
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((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
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#define WAKEMASK(gpio) \
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(((gpio) <= 15) \
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? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
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: ((gpio == 35) ? (1 << 24) : 0))
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#else
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/* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */
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#define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0)
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#endif
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/*
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* PXA GPIO edge detection for IRQs:
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* IRQs are generated on Falling-Edge, Rising-Edge, or both.
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* Use this instead of directly setting GRER/GFER.
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*/
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static long GPIO_IRQ_rising_edge[4];
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static long GPIO_IRQ_falling_edge[4];
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static long GPIO_IRQ_mask[4];
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static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
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{
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int gpio, idx;
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u32 mask;
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gpio = IRQ_TO_GPIO(irq);
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idx = gpio >> 5;
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mask = WAKEMASK(gpio);
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if (type == IRQT_PROBE) {
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/* Don't mess with enabled GPIOs using preconfigured edges or
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GPIOs set to alternate function or to output during probe */
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if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) &
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GPIO_bit(gpio))
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return 0;
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if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
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return 0;
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type = __IRQT_RISEDGE | __IRQT_FALEDGE;
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}
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/* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
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pxa_gpio_mode(gpio | GPIO_IN);
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if (type & __IRQT_RISEDGE) {
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/* printk("rising "); */
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__set_bit (gpio, GPIO_IRQ_rising_edge);
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PRER |= mask;
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} else {
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__clear_bit (gpio, GPIO_IRQ_rising_edge);
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PRER &= ~mask;
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}
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if (type & __IRQT_FALEDGE) {
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/* printk("falling "); */
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__set_bit (gpio, GPIO_IRQ_falling_edge);
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PFER |= mask;
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} else {
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__clear_bit (gpio, GPIO_IRQ_falling_edge);
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PFER &= ~mask;
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}
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/* printk("edges\n"); */
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GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
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GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
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return 0;
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}
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/*
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* GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
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*/
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static void pxa_ack_low_gpio(unsigned int irq)
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{
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GEDR0 = (1 << (irq - IRQ_GPIO0));
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}
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static int pxa_set_gpio_wake(unsigned int irq, unsigned int on)
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{
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int gpio = IRQ_TO_GPIO(irq);
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u32 mask = WAKEMASK(gpio);
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if (!mask)
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return -EINVAL;
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if (on)
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PWER |= mask;
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else
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PWER &= ~mask;
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return 0;
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}
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static struct irq_chip pxa_low_gpio_chip = {
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.name = "GPIO-l",
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.ack = pxa_ack_low_gpio,
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.mask = pxa_mask_low_irq,
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.unmask = pxa_unmask_low_irq,
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.set_type = pxa_gpio_irq_type,
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.set_wake = pxa_set_gpio_wake,
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};
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/*
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* Demux handler for GPIO>=2 edge detect interrupts
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*/
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static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int mask;
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int loop;
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do {
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loop = 0;
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mask = GEDR0 & GPIO_IRQ_mask[0] & ~3;
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if (mask) {
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GEDR0 = mask;
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irq = IRQ_GPIO(2);
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desc = irq_desc + irq;
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mask >>= 2;
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do {
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if (mask & 1)
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desc_handle_irq(irq, desc);
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irq++;
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desc++;
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mask >>= 1;
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} while (mask);
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loop = 1;
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}
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mask = GEDR1 & GPIO_IRQ_mask[1];
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if (mask) {
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GEDR1 = mask;
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irq = IRQ_GPIO(32);
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desc = irq_desc + irq;
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do {
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if (mask & 1)
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desc_handle_irq(irq, desc);
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irq++;
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desc++;
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mask >>= 1;
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} while (mask);
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loop = 1;
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}
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mask = GEDR2 & GPIO_IRQ_mask[2];
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if (mask) {
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GEDR2 = mask;
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irq = IRQ_GPIO(64);
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desc = irq_desc + irq;
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do {
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if (mask & 1)
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desc_handle_irq(irq, desc);
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irq++;
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desc++;
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mask >>= 1;
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} while (mask);
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loop = 1;
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}
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mask = GEDR3 & GPIO_IRQ_mask[3];
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if (mask) {
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GEDR3 = mask;
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irq = IRQ_GPIO(96);
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desc = irq_desc + irq;
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do {
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if (mask & 1)
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desc_handle_irq(irq, desc);
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irq++;
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desc++;
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mask >>= 1;
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} while (mask);
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loop = 1;
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}
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} while (loop);
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}
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static void pxa_ack_muxed_gpio(unsigned int irq)
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{
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int gpio = irq - IRQ_GPIO(2) + 2;
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GEDR(gpio) = GPIO_bit(gpio);
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}
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static void pxa_mask_muxed_gpio(unsigned int irq)
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{
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int gpio = irq - IRQ_GPIO(2) + 2;
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__clear_bit(gpio, GPIO_IRQ_mask);
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GRER(gpio) &= ~GPIO_bit(gpio);
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GFER(gpio) &= ~GPIO_bit(gpio);
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}
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static void pxa_unmask_muxed_gpio(unsigned int irq)
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{
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int gpio = irq - IRQ_GPIO(2) + 2;
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int idx = gpio >> 5;
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__set_bit(gpio, GPIO_IRQ_mask);
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GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
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GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
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}
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static struct irq_chip pxa_muxed_gpio_chip = {
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.name = "GPIO",
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.ack = pxa_ack_muxed_gpio,
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.mask = pxa_mask_muxed_gpio,
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.unmask = pxa_unmask_muxed_gpio,
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.set_type = pxa_gpio_irq_type,
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.set_wake = pxa_set_gpio_wake,
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};
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void __init pxa_init_irq_gpio(int gpio_nr)
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{
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int irq, i;
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/* clear all GPIO edge detects */
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for (i = 0; i < gpio_nr; i += 32) {
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GFER(i) = 0;
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GRER(i) = 0;
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GEDR(i) = GEDR(i);
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}
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/* GPIO 0 and 1 must have their mask bit always set */
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GPIO_IRQ_mask[0] = 3;
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for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
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set_irq_chip(irq, &pxa_low_gpio_chip);
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set_irq_handler(irq, handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(gpio_nr); irq++) {
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set_irq_chip(irq, &pxa_muxed_gpio_chip);
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set_irq_handler(irq, handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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/* Install handler for GPIO>=2 edge detect interrupts */
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set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
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set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
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}
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void __init pxa_init_irq(void)
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{
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pxa_init_irq_low();
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#ifdef CONFIG_PXA27x
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pxa_init_irq_high();
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#endif
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pxa_init_irq_gpio(PXA_LAST_GPIO + 1);
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}
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