8a9e1b0f56
Issue: Current tsc based delay_calibration can result in significant errors in loops_per_jiffy count when the platform events like SMIs (System Management Interrupts that are non-maskable) are present. This could lead to potential kernel panic(). This issue is becoming more visible with 2.6 kernel (as default HZ is 1000) and on platforms with higher SMI handling latencies. During the boot time, SMIs are mostly used by BIOS (for things like legacy keyboard emulation). Description: The psuedocode for current delay calibration with tsc based delay looks like (0) Estimate a value for loops_per_jiffy (1) While (loops_per_jiffy estimate is accurate enough) (2) wait for jiffy transition (jiffy1) (3) Note down current tsc (tsc1) (4) loop until tsc becomes tsc1 + loops_per_jiffy (5) check whether jiffy changed since jiffy1 or not and refine loops_per_jiffy estimate Consider the following cases Case 1: If SMIs happen between (2) and (3) above, we can end up with a loops_per_jiffy value that is too low. This results in shorted delays and kernel can panic () during boot (Mostly at IOAPIC timer initialization timer_irq_works() as we don't have enough timer interrupts in a specified interval). Case 2: If SMIs happen between (3) and (4) above, then we can end up with a loops_per_jiffy value that is too high. And with current i386 code, too high lpj value (greater than 17M) can result in a overflow in delay.c:__const_udelay() again resulting in shorter delay and panic(). Solution: The patch below makes the calibration routine aware of asynchronous events like SMIs. We increase the delay calibration time and also identify any significant errors (greater than 12.5%) in the calibration and notify it to user. Patch below changes both i386 and x86-64 architectures to use this new and improved calibrate_delay_direct() routine. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
56 lines
1.3 KiB
C
56 lines
1.3 KiB
C
/*
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* linux/include/asm-i386/timex.h
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*
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* i386 architecture timex specifications
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*/
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#ifndef _ASMi386_TIMEX_H
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#define _ASMi386_TIMEX_H
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#include <linux/config.h>
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#include <asm/processor.h>
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#ifdef CONFIG_X86_ELAN
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# define CLOCK_TICK_RATE 1189200 /* AMD Elan has different frequency! */
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#else
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# define CLOCK_TICK_RATE 1193182 /* Underlying HZ */
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#endif
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/*
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* Standard way to access the cycle counter on i586+ CPUs.
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* Currently only used on SMP.
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*
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* If you really have a SMP machine with i486 chips or older,
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* compile for that, and this will just always return zero.
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* That's ok, it just means that the nicer scheduling heuristics
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* won't work for you.
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*
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* We only use the low 32 bits, and we'd simply better make sure
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* that we reschedule before that wraps. Scheduling at least every
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* four billion cycles just basically sounds like a good idea,
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* regardless of how fast the machine is.
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*/
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typedef unsigned long long cycles_t;
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static inline cycles_t get_cycles (void)
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{
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unsigned long long ret=0;
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#ifndef CONFIG_X86_TSC
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if (!cpu_has_tsc)
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return 0;
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#endif
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#if defined(CONFIG_X86_GENERIC) || defined(CONFIG_X86_TSC)
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rdtscll(ret);
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#endif
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return ret;
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}
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extern unsigned long cpu_khz;
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extern int read_current_timer(unsigned long *timer_value);
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#define ARCH_HAS_READ_CURRENT_TIMER 1
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#endif
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