1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
159 lines
5.6 KiB
C
159 lines
5.6 KiB
C
/*
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* include/asm-v850/as85ep1.h -- AS85EP1 evaluation CPU chip/board
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_AS85EP1_H__
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#define __V850_AS85EP1_H__
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#include <asm/v850e.h>
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#define CPU_MODEL "as85ep1"
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#define CPU_MODEL_LONG "NEC V850E/AS85EP1"
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#define PLATFORM "AS85EP1"
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#define PLATFORM_LONG "NEC V850E/AS85EP1 evaluation board"
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#define CPU_CLOCK_FREQ 96000000 /* 96MHz */
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#define SYS_CLOCK_FREQ CPU_CLOCK_FREQ
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/* 1MB of static RAM. */
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#define SRAM_ADDR 0x00400000
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#define SRAM_SIZE 0x00100000 /* 1MB */
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/* About 58MB of DRAM. This can actually be at one of two positions,
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determined by jump JP3; we have to use the first position because the
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second is partially out of processor instruction addressing range
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(though in the second position there's actually 64MB available). */
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#define SDRAM_ADDR 0x00600000
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#define SDRAM_SIZE 0x039F8000 /* approx 58MB */
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/* For <asm/page.h> */
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#define PAGE_OFFSET SRAM_ADDR
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/* We use on-chip RAM, for a few miscellaneous variables that must be
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accessible using a load instruction relative to R0. The AS85EP1 chip
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16K of internal RAM located slightly before I/O space. */
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#define R0_RAM_ADDR 0xFFFF8000
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/* AS85EP1 specific control registers. */
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#define AS85EP1_CSC_ADDR(n) (0xFFFFF060 + (n) * 2)
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#define AS85EP1_CSC(n) (*(volatile u16 *)AS85EP1_CSC_ADDR(n))
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#define AS85EP1_BSC_ADDR 0xFFFFF066
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#define AS85EP1_BSC (*(volatile u16 *)AS85EP1_BSC_ADDR)
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#define AS85EP1_BCT_ADDR(n) (0xFFFFF480 + (n) * 2)
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#define AS85EP1_BCT(n) (*(volatile u16 *)AS85EP1_BCT_ADDR(n))
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#define AS85EP1_DWC_ADDR(n) (0xFFFFF484 + (n) * 2)
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#define AS85EP1_DWC(n) (*(volatile u16 *)AS85EP1_DWC_ADDR(n))
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#define AS85EP1_BCC_ADDR 0xFFFFF488
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#define AS85EP1_BCC (*(volatile u16 *)AS85EP1_BCC_ADDR)
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#define AS85EP1_ASC_ADDR 0xFFFFF48A
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#define AS85EP1_ASC (*(volatile u16 *)AS85EP1_ASC_ADDR)
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#define AS85EP1_BCP_ADDR 0xFFFFF48C
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#define AS85EP1_BCP (*(volatile u16 *)AS85EP1_BCP_ADDR)
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#define AS85EP1_LBS_ADDR 0xFFFFF48E
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#define AS85EP1_LBS (*(volatile u16 *)AS85EP1_LBS_ADDR)
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#define AS85EP1_BMC_ADDR 0xFFFFF498
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#define AS85EP1_BMC (*(volatile u16 *)AS85EP1_BMC_ADDR)
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#define AS85EP1_PRC_ADDR 0xFFFFF49A
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#define AS85EP1_PRC (*(volatile u16 *)AS85EP1_PRC_ADDR)
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#define AS85EP1_SCR_ADDR(n) (0xFFFFF4A0 + (n) * 4)
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#define AS85EP1_SCR(n) (*(volatile u16 *)AS85EP1_SCR_ADDR(n))
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#define AS85EP1_RFS_ADDR(n) (0xFFFFF4A2 + (n) * 4)
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#define AS85EP1_RFS(n) (*(volatile u16 *)AS85EP1_RFS_ADDR(n))
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#define AS85EP1_IRAMM_ADDR 0xFFFFF80A
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#define AS85EP1_IRAMM (*(volatile u8 *)AS85EP1_IRAMM_ADDR)
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/* I/O port P0-P13. */
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/* Direct I/O. Bits 0-7 are pins Pn0-Pn7. */
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#define AS85EP1_PORT_IO_ADDR(n) (0xFFFFF400 + (n) * 2)
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#define AS85EP1_PORT_IO(n) (*(volatile u8 *)AS85EP1_PORT_IO_ADDR(n))
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/* Port mode (for direct I/O, 0 = output, 1 = input). */
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#define AS85EP1_PORT_PM_ADDR(n) (0xFFFFF420 + (n) * 2)
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#define AS85EP1_PORT_PM(n) (*(volatile u8 *)AS85EP1_PORT_PM_ADDR(n))
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/* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
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#define AS85EP1_PORT_PMC_ADDR(n) (0xFFFFF440 + (n) * 2)
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#define AS85EP1_PORT_PMC(n) (*(volatile u8 *)AS85EP1_PORT_PMC_ADDR(n))
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/* Hardware-specific interrupt numbers (in the kernel IRQ namespace). */
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#define IRQ_INTCCC(n) (0x0C + (n))
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#define IRQ_INTCCC_NUM 8
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#define IRQ_INTCMD(n) (0x14 + (n)) /* interval timer interrupts 0-5 */
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#define IRQ_INTCMD_NUM 6
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#define IRQ_INTSRE(n) (0x1E + (n)*3) /* UART 0-1 reception error */
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#define IRQ_INTSRE_NUM 2
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#define IRQ_INTSR(n) (0x1F + (n)*3) /* UART 0-1 reception completion */
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#define IRQ_INTSR_NUM 2
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#define IRQ_INTST(n) (0x20 + (n)*3) /* UART 0-1 transmission completion */
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#define IRQ_INTST_NUM 2
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#define NUM_CPU_IRQS 64
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#ifndef __ASSEMBLY__
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/* Initialize chip interrupts. */
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extern void as85ep1_init_irqs (void);
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#endif
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/* AS85EP1 UART details (basically the same as the V850E/MA1, but 2 channels). */
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#define V850E_UART_NUM_CHANNELS 2
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#define V850E_UART_BASE_FREQ (SYS_CLOCK_FREQ / 4)
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#define V850E_UART_CHIP_NAME "V850E/NA85E"
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/* This is a function that gets called before configuring the UART. */
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#define V850E_UART_PRE_CONFIGURE as85ep1_uart_pre_configure
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#ifndef __ASSEMBLY__
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extern void as85ep1_uart_pre_configure (unsigned chan,
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unsigned cflags, unsigned baud);
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#endif
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/* This board supports RTS/CTS for the on-chip UART, but only for channel 1. */
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/* CTS for UART channel 1 is pin P54 (bit 4 of port 5). */
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#define V850E_UART_CTS(chan) ((chan) == 1 ? !(AS85EP1_PORT_IO(5) & 0x10) : 1)
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/* RTS for UART channel 1 is pin P53 (bit 3 of port 5). */
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#define V850E_UART_SET_RTS(chan, val) \
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do { \
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if (chan == 1) { \
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unsigned old = AS85EP1_PORT_IO(5); \
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if (val) \
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AS85EP1_PORT_IO(5) = old & ~0x8; \
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else \
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AS85EP1_PORT_IO(5) = old | 0x8; \
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} \
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} while (0)
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/* Timer C details. */
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#define V850E_TIMER_C_BASE_ADDR 0xFFFFF600
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/* Timer D details (the AS85EP1 actually has 5 of these; should change later). */
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#define V850E_TIMER_D_BASE_ADDR 0xFFFFF540
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#define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
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#define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x2)
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#define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
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#define V850E_TIMER_D_BASE_FREQ SYS_CLOCK_FREQ
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#define V850E_TIMER_D_TMCD_CS_MIN 2 /* min 2^2 divider */
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/* For <asm/param.h> */
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#ifndef HZ
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#define HZ 100
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#endif
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#endif /* __V850_AS85EP1_H__ */
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