bd0b9ac405
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
146 lines
3.6 KiB
C
146 lines
3.6 KiB
C
/*
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* bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
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*
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* All Alchemy development boards (except, of course, the weird PB1000)
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* have a few registers in a CPLD with standardised layout; they mostly
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* only differ in base address.
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* All registers are 16bits wide with 32bit spacing.
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*/
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/irq.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/mach-db1x00/bcsr.h>
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static struct bcsr_reg {
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void __iomem *raddr;
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spinlock_t lock;
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} bcsr_regs[BCSR_CNT];
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static void __iomem *bcsr_virt; /* KSEG1 addr of BCSR base */
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static int bcsr_csc_base; /* linux-irq of first cascaded irq */
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void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)
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{
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int i;
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bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys));
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bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys));
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bcsr_virt = (void __iomem *)bcsr1_phys;
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for (i = 0; i < BCSR_CNT; i++) {
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if (i >= BCSR_HEXLEDS)
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bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys +
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(0x04 * (i - BCSR_HEXLEDS));
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else
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bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys +
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(0x04 * i);
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spin_lock_init(&bcsr_regs[i].lock);
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}
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}
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unsigned short bcsr_read(enum bcsr_id reg)
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{
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unsigned short r;
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unsigned long flags;
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spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
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r = __raw_readw(bcsr_regs[reg].raddr);
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spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
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return r;
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}
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EXPORT_SYMBOL_GPL(bcsr_read);
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void bcsr_write(enum bcsr_id reg, unsigned short val)
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{
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unsigned long flags;
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spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
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__raw_writew(val, bcsr_regs[reg].raddr);
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wmb();
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spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
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}
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EXPORT_SYMBOL_GPL(bcsr_write);
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void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set)
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{
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unsigned short r;
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unsigned long flags;
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spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
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r = __raw_readw(bcsr_regs[reg].raddr);
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r &= ~clr;
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r |= set;
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__raw_writew(r, bcsr_regs[reg].raddr);
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wmb();
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spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
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}
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EXPORT_SYMBOL_GPL(bcsr_mod);
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/*
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* DB1200/PB1200 CPLD IRQ muxer
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*/
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static void bcsr_csc_handler(struct irq_desc *d)
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{
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unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
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struct irq_chip *chip = irq_desc_get_chip(d);
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chained_irq_enter(chip, d);
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generic_handle_irq(bcsr_csc_base + __ffs(bisr));
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chained_irq_exit(chip, d);
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}
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static void bcsr_irq_mask(struct irq_data *d)
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{
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unsigned short v = 1 << (d->irq - bcsr_csc_base);
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__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
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wmb();
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}
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static void bcsr_irq_maskack(struct irq_data *d)
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{
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unsigned short v = 1 << (d->irq - bcsr_csc_base);
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__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
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__raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
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wmb();
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}
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static void bcsr_irq_unmask(struct irq_data *d)
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{
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unsigned short v = 1 << (d->irq - bcsr_csc_base);
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__raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
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wmb();
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}
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static struct irq_chip bcsr_irq_type = {
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.name = "CPLD",
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.irq_mask = bcsr_irq_mask,
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.irq_mask_ack = bcsr_irq_maskack,
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.irq_unmask = bcsr_irq_unmask,
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};
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void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
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{
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unsigned int irq;
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/* mask & enable & ack all */
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__raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
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__raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET);
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__raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
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wmb();
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bcsr_csc_base = csc_start;
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for (irq = csc_start; irq <= csc_end; irq++)
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irq_set_chip_and_handler_name(irq, &bcsr_irq_type,
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handle_level_irq, "level");
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irq_set_chained_handler(hook_irq, bcsr_csc_handler);
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}
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