498900fc9c
Architectures that handle DMA-non-coherent memory need to set ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is DMA-safe: the buffer doesn't share a cache with the others. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Cc: Chris Zankel <chris@zankel.net> Acked-by: Pekka Enberg <penberg@cs.helsinki.fi> Cc: <stable@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
35 lines
973 B
C
35 lines
973 B
C
/*
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* include/asm-xtensa/cache.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_CACHE_H
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#define _XTENSA_CACHE_H
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#include <variant/core.h>
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#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH
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#define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
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#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
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#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
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#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
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/* Maximum cache size per way. */
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#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE
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# define CACHE_WAY_SIZE DCACHE_WAY_SIZE
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#else
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# define CACHE_WAY_SIZE ICACHE_WAY_SIZE
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#endif
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#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
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#endif /* _XTENSA_CACHE_H */
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