10dd5ce28d
set_irq_chipdata -> set_irq_chip_data get_irq_chipdata -> get_irq_chip_data do_level_IRQ -> handle_level_irq do_edge_IRQ -> handle_edge_irq do_simple_IRQ -> handle_simple_irq irqdesc -> irq_desc irqchip -> irq_chip Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
99 lines
2.6 KiB
C
99 lines
2.6 KiB
C
/*
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* linux/arch/arm/common/vic.c
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*
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* Copyright (C) 1999 - 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/list.h>
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#include <asm/io.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/vic.h>
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static void vic_mask_irq(unsigned int irq)
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{
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void __iomem *base = get_irq_chip_data(irq);
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irq &= 31;
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writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
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}
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static void vic_unmask_irq(unsigned int irq)
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{
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void __iomem *base = get_irq_chip_data(irq);
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irq &= 31;
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writel(1 << irq, base + VIC_INT_ENABLE);
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}
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static struct irq_chip vic_chip = {
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.name = "VIC",
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.ack = vic_mask_irq,
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.mask = vic_mask_irq,
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.unmask = vic_unmask_irq,
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};
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/**
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* vic_init - initialise a vectored interrupt controller
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* @base: iomem base address
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* @irq_start: starting interrupt number, must be muliple of 32
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* @vic_sources: bitmask of interrupt sources to allow
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*/
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void __init vic_init(void __iomem *base, unsigned int irq_start,
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u32 vic_sources)
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{
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unsigned int i;
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/* Disable all interrupts initially. */
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writel(0, base + VIC_INT_SELECT);
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writel(0, base + VIC_INT_ENABLE);
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writel(~0, base + VIC_INT_ENABLE_CLEAR);
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writel(0, base + VIC_IRQ_STATUS);
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writel(0, base + VIC_ITCR);
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writel(~0, base + VIC_INT_SOFT_CLEAR);
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/*
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* Make sure we clear all existing interrupts
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*/
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writel(0, base + VIC_VECT_ADDR);
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for (i = 0; i < 19; i++) {
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unsigned int value;
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value = readl(base + VIC_VECT_ADDR);
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writel(value, base + VIC_VECT_ADDR);
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}
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for (i = 0; i < 16; i++) {
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void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
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writel(VIC_VECT_CNTL_ENABLE | i, reg);
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}
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writel(32, base + VIC_DEF_VECT_ADDR);
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for (i = 0; i < 32; i++) {
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unsigned int irq = irq_start + i;
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set_irq_chip(irq, &vic_chip);
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set_irq_chip_data(irq, base);
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if (vic_sources & (1 << i)) {
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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}
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}
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