Venkatesh Pallipadi 434440a280 [PATCH] x86: bug fix in P6 Machine check initialization ... Make P6 MCA initialization code complaint with guidelines in IA-32 SDM Vol3. Bank 0 control register should not be set by OS and clear status registers on all banks on reset. This will prevent false MCE alarms on the systems that has some non-MCE information left-over in MC0_STATUS on reboot. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>		2005-10-30 17:37:12 -08:00
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cpufreq
mcheck	[PATCH] x86: bug fix in P6 Machine check initialization	2005-10-30 17:37:12 -08:00
mtrr
amd.c
centaur.c
changelog
common.c	[PATCH] x86: add an accessor function for getting the per-CPU gdt	2005-10-30 17:37:12 -08:00
cpu.h
cyrix.c
intel_cacheinfo.c	[PATCH] intel_cacheinfo: remove MAX_CACHE_LEAVES limit	2005-10-30 17:37:11 -08:00
intel.c
Makefile
nexgen.c
proc.c
rise.c
transmeta.c
umc.c