6a1c53124a
TPIDRURW is a user read/write register forming part of the group of thread registers in more recent versions of the ARM architecture (~v6+). Currently, the kernel does not touch this register, which allows tasks to communicate covertly by reading and writing to the register without context-switching affecting its contents. This patch clears TPIDRURW when TPIDRURO is updated via the set_tls macro, which is called directly from __switch_to. Since the current behaviour makes the register useless to userspace as far as thread pointers are concerned, simply clearing the register (rather than saving and restoring it) will not cause any problems to userspace. Cc: stable@vger.kernel.org Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
#ifndef __ASMARM_TLS_H
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#define __ASMARM_TLS_H
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#ifdef __ASSEMBLY__
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.macro set_tls_none, tp, tmp1, tmp2
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.endm
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.macro set_tls_v6k, tp, tmp1, tmp2
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mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
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mov \tmp1, #0
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mcr p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
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.endm
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.macro set_tls_v6, tp, tmp1, tmp2
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ldr \tmp1, =elf_hwcap
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ldr \tmp1, [\tmp1, #0]
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mov \tmp2, #0xffff0fff
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tst \tmp1, #HWCAP_TLS @ hardware TLS available?
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mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
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movne \tmp1, #0
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mcrne p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
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streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
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.endm
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.macro set_tls_software, tp, tmp1, tmp2
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mov \tmp1, #0xffff0fff
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str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0
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.endm
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#endif
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#ifdef CONFIG_TLS_REG_EMUL
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#define tls_emu 1
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#define has_tls_reg 1
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#define set_tls set_tls_none
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#elif defined(CONFIG_CPU_V6)
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#define tls_emu 0
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#define has_tls_reg (elf_hwcap & HWCAP_TLS)
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#define set_tls set_tls_v6
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#elif defined(CONFIG_CPU_32v6K)
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#define tls_emu 0
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#define has_tls_reg 1
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#define set_tls set_tls_v6k
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#else
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#define tls_emu 0
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#define has_tls_reg 0
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#define set_tls set_tls_software
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#endif
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#endif /* __ASMARM_TLS_H */
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