3c739ad0df
This patch enables mapping a base offset of gpio ranges with
a pin offset even if does'nt matched. A base of pinctrl_gpio_range
means a base offset of gpio. However, we cannot convert gpio to pin
number for sparse gpio ranges just only using a gpio base offset.
We can convert a gpio to real pin number(even if not matched) using
a new pin_base which means a base pin offset of requested gpio range.
Now, the pin control subsystem passes the pin base offset to the
pinmux driver.
For example, let's assume below two gpio ranges in the system.
static struct pinctrl_gpio_range gpio_range_a = {
.name = "chip a",
.id = 0,
.base = 32,
.pin_base = 32,
.npins = 16,
.gc = &chip_a;
};
static struct pinctrl_gpio_range gpio_range_b = {
.name = "chip b",
.id = 0,
.base = 48,
.pin_base = 64,
.npins = 8,
.gc = &chip_b;
};
We can calucalate a exact pin ranges even if doesn't matched with gpio ranges.
chip a:
gpio-range : [32 .. 47]
pin-range : [32 .. 47]
chip b:
gpio-range : [48 .. 55]
pin-range : [64 .. 71]
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
121 lines
4.3 KiB
C
121 lines
4.3 KiB
C
/*
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* Interface the pinmux subsystem
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*
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* Copyright (C) 2011 ST-Ericsson SA
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* Written on behalf of Linaro for ST-Ericsson
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* Based on bits of regulator core, gpio core and clk core
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*
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* Author: Linus Walleij <linus.walleij@linaro.org>
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef __LINUX_PINCTRL_PINMUX_H
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#define __LINUX_PINCTRL_PINMUX_H
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#include <linux/list.h>
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#include <linux/seq_file.h>
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#include "pinctrl.h"
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/* This struct is private to the core and should be regarded as a cookie */
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struct pinmux;
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#ifdef CONFIG_PINMUX
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struct pinctrl_dev;
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/**
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* struct pinmux_ops - pinmux operations, to be implemented by pin controller
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* drivers that support pinmuxing
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* @request: called by the core to see if a certain pin can be made available
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* available for muxing. This is called by the core to acquire the pins
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* before selecting any actual mux setting across a function. The driver
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* is allowed to answer "no" by returning a negative error code
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* @free: the reverse function of the request() callback, frees a pin after
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* being requested
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* @list_functions: list the number of selectable named functions available
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* in this pinmux driver, the core will begin on 0 and call this
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* repeatedly as long as it returns >= 0 to enumerate mux settings
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* @get_function_name: return the function name of the muxing selector,
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* called by the core to figure out which mux setting it shall map a
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* certain device to
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* @get_function_groups: return an array of groups names (in turn
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* referencing pins) connected to a certain function selector. The group
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* name can be used with the generic @pinctrl_ops to retrieve the
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* actual pins affected. The applicable groups will be returned in
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* @groups and the number of groups in @num_groups
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* @enable: enable a certain muxing function with a certain pin group. The
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* driver does not need to figure out whether enabling this function
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* conflicts some other use of the pins in that group, such collisions
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* are handled by the pinmux subsystem. The @func_selector selects a
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* certain function whereas @group_selector selects a certain set of pins
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* to be used. On simple controllers the latter argument may be ignored
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* @disable: disable a certain muxing selector with a certain pin group
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* @gpio_request_enable: requests and enables GPIO on a certain pin.
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* Implement this only if you can mux every pin individually as GPIO. The
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* affected GPIO range is passed along with an offset(pin number) into that
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* specific GPIO range - function selectors and pin groups are orthogonal
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* to this, the core will however make sure the pins do not collide
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*/
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struct pinmux_ops {
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int (*request) (struct pinctrl_dev *pctldev, unsigned offset);
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int (*free) (struct pinctrl_dev *pctldev, unsigned offset);
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int (*list_functions) (struct pinctrl_dev *pctldev, unsigned selector);
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const char *(*get_function_name) (struct pinctrl_dev *pctldev,
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unsigned selector);
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int (*get_function_groups) (struct pinctrl_dev *pctldev,
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unsigned selector,
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const char * const **groups,
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unsigned * const num_groups);
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int (*enable) (struct pinctrl_dev *pctldev, unsigned func_selector,
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unsigned group_selector);
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void (*disable) (struct pinctrl_dev *pctldev, unsigned func_selector,
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unsigned group_selector);
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int (*gpio_request_enable) (struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset);
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void (*gpio_disable_free) (struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset);
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};
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/* External interface to pinmux */
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extern int pinmux_request_gpio(unsigned gpio);
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extern void pinmux_free_gpio(unsigned gpio);
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extern struct pinmux * __must_check pinmux_get(struct device *dev, const char *name);
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extern void pinmux_put(struct pinmux *pmx);
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extern int pinmux_enable(struct pinmux *pmx);
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extern void pinmux_disable(struct pinmux *pmx);
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#else /* !CONFIG_PINMUX */
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static inline int pinmux_request_gpio(unsigned gpio)
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{
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return 0;
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}
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static inline void pinmux_free_gpio(unsigned gpio)
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{
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}
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static inline struct pinmux * __must_check pinmux_get(struct device *dev, const char *name)
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{
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return NULL;
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}
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static inline void pinmux_put(struct pinmux *pmx)
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{
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}
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static inline int pinmux_enable(struct pinmux *pmx)
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{
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return 0;
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}
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static inline void pinmux_disable(struct pinmux *pmx)
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{
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}
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#endif /* CONFIG_PINMUX */
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#endif /* __LINUX_PINCTRL_PINMUX_H */
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