3a63833ec3
wires variable is renamed, extended and this single variable to be used to pass the platform capabilities, e.g DDR mode. Also removed the hardcoded value was using as bus-width. Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
366 lines
9.8 KiB
C
366 lines
9.8 KiB
C
/*
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* linux/arch/arm/mach-omap2/hsmmc.c
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*
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* Copyright (C) 2007-2008 Texas Instruments
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* Copyright (C) 2008 Nokia Corporation
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* Author: Texas Instruments
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <mach/hardware.h>
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#include <plat/control.h>
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#include <plat/mmc.h>
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#include <plat/omap-pm.h>
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#include "hsmmc.h"
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#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
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static u16 control_pbias_offset;
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static u16 control_devconf1_offset;
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static u16 control_mmc1;
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#define HSMMC_NAME_LEN 9
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static struct hsmmc_controller {
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char name[HSMMC_NAME_LEN + 1];
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} hsmmc[OMAP34XX_NR_MMC];
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
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static int hsmmc_get_context_loss(struct device *dev)
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{
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return omap_pm_get_dev_context_loss_count(dev);
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}
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#else
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#define hsmmc_get_context_loss NULL
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#endif
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static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
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int power_on, int vdd)
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{
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u32 reg, prog_io;
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struct omap_mmc_platform_data *mmc = dev->platform_data;
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if (mmc->slots[0].remux)
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mmc->slots[0].remux(dev, slot, power_on);
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/*
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* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
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* card with Vcc regulator (from twl4030 or whatever). OMAP has both
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* 1.8V and 3.0V modes, controlled by the PBIAS register.
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*
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* In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
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* is most naturally TWL VSIM; those pins also use PBIAS.
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*
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* FIXME handle VMMC1A as needed ...
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*/
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if (power_on) {
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if (cpu_is_omap2430()) {
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reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
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if ((1 << vdd) >= MMC_VDD_30_31)
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reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
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else
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reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
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omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
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}
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if (mmc->slots[0].internal_clock) {
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reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
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reg |= OMAP2_MMCSDIO1ADPCLKISEL;
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omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
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}
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reg = omap_ctrl_readl(control_pbias_offset);
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if (cpu_is_omap3630()) {
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/* Set MMC I/O to 52Mhz */
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prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
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prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
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omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
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} else {
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reg |= OMAP2_PBIASSPEEDCTRL0;
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}
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reg &= ~OMAP2_PBIASLITEPWRDNZ0;
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omap_ctrl_writel(reg, control_pbias_offset);
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} else {
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reg = omap_ctrl_readl(control_pbias_offset);
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reg &= ~OMAP2_PBIASLITEPWRDNZ0;
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omap_ctrl_writel(reg, control_pbias_offset);
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}
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}
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static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
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int power_on, int vdd)
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{
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u32 reg;
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/* 100ms delay required for PBIAS configuration */
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msleep(100);
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if (power_on) {
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reg = omap_ctrl_readl(control_pbias_offset);
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reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
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if ((1 << vdd) <= MMC_VDD_165_195)
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reg &= ~OMAP2_PBIASLITEVMODE0;
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else
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reg |= OMAP2_PBIASLITEVMODE0;
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omap_ctrl_writel(reg, control_pbias_offset);
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} else {
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reg = omap_ctrl_readl(control_pbias_offset);
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reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
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OMAP2_PBIASLITEVMODE0);
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omap_ctrl_writel(reg, control_pbias_offset);
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}
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}
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static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
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int power_on, int vdd)
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{
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u32 reg;
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/*
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* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
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* card with Vcc regulator (from twl4030 or whatever). OMAP has both
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* 1.8V and 3.0V modes, controlled by the PBIAS register.
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*
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* In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
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* is most naturally TWL VSIM; those pins also use PBIAS.
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*
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* FIXME handle VMMC1A as needed ...
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*/
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reg = omap_ctrl_readl(control_pbias_offset);
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reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
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OMAP4_USBC1_ICUSB_PWRDNZ);
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omap_ctrl_writel(reg, control_pbias_offset);
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}
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static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
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int power_on, int vdd)
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{
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u32 reg;
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if (power_on) {
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reg = omap_ctrl_readl(control_pbias_offset);
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reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ;
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if ((1 << vdd) <= MMC_VDD_165_195)
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reg &= ~OMAP4_MMC1_PBIASLITE_VMODE;
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else
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reg |= OMAP4_MMC1_PBIASLITE_VMODE;
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reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
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OMAP4_USBC1_ICUSB_PWRDNZ);
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omap_ctrl_writel(reg, control_pbias_offset);
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/* 4 microsec delay for comparator to generate an error*/
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udelay(4);
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reg = omap_ctrl_readl(control_pbias_offset);
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if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) {
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pr_err("Pbias Voltage is not same as LDO\n");
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/* Caution : On VMODE_ERROR Power Down MMC IO */
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reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ);
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omap_ctrl_writel(reg, control_pbias_offset);
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}
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} else {
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reg = omap_ctrl_readl(control_pbias_offset);
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reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ |
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OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ |
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OMAP4_USBC1_ICUSB_PWRDNZ);
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omap_ctrl_writel(reg, control_pbias_offset);
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}
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}
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static void hsmmc23_before_set_reg(struct device *dev, int slot,
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int power_on, int vdd)
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{
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struct omap_mmc_platform_data *mmc = dev->platform_data;
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if (mmc->slots[0].remux)
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mmc->slots[0].remux(dev, slot, power_on);
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if (power_on) {
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/* Only MMC2 supports a CLKIN */
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if (mmc->slots[0].internal_clock) {
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u32 reg;
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reg = omap_ctrl_readl(control_devconf1_offset);
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reg |= OMAP2_MMCSDIO2ADPCLKISEL;
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omap_ctrl_writel(reg, control_devconf1_offset);
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}
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}
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}
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static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
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int vdd)
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{
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return 0;
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}
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static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
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void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
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{
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struct omap2_hsmmc_info *c;
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int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
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int i;
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u32 reg;
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if (!cpu_is_omap44xx()) {
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if (cpu_is_omap2430()) {
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control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
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control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
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} else {
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control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
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control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
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}
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} else {
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control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE;
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control_mmc1 = OMAP44XX_CONTROL_MMC1;
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reg = omap_ctrl_readl(control_mmc1);
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reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 |
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OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1);
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reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 |
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OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3);
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reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL |
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OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL |
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OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL);
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omap_ctrl_writel(reg, control_mmc1);
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}
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for (c = controllers; c->mmc; c++) {
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struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
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struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
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if (!c->mmc || c->mmc > nr_hsmmc) {
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pr_debug("MMC%d: no such controller\n", c->mmc);
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continue;
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}
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if (mmc) {
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pr_debug("MMC%d: already configured\n", c->mmc);
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continue;
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}
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mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
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GFP_KERNEL);
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if (!mmc) {
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pr_err("Cannot allocate memory for mmc device!\n");
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goto done;
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}
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if (c->name)
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strncpy(hc->name, c->name, HSMMC_NAME_LEN);
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else
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snprintf(hc->name, ARRAY_SIZE(hc->name),
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"mmc%islot%i", c->mmc, 1);
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mmc->slots[0].name = hc->name;
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mmc->nr_slots = 1;
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mmc->slots[0].caps = c->caps;
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mmc->slots[0].internal_clock = !c->ext_clock;
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mmc->dma_mask = 0xffffffff;
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mmc->get_context_loss_count = hsmmc_get_context_loss;
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mmc->slots[0].switch_pin = c->gpio_cd;
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mmc->slots[0].gpio_wp = c->gpio_wp;
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mmc->slots[0].remux = c->remux;
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mmc->slots[0].init_card = c->init_card;
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if (c->cover_only)
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mmc->slots[0].cover = 1;
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if (c->nonremovable)
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mmc->slots[0].nonremovable = 1;
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if (c->power_saving)
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mmc->slots[0].power_saving = 1;
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if (c->no_off)
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mmc->slots[0].no_off = 1;
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if (c->vcc_aux_disable_is_sleep)
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mmc->slots[0].vcc_aux_disable_is_sleep = 1;
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/* NOTE: MMC slots should have a Vcc regulator set up.
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* This may be from a TWL4030-family chip, another
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* controllable regulator, or a fixed supply.
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*
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* temporary HACK: ocr_mask instead of fixed supply
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*/
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mmc->slots[0].ocr_mask = c->ocr_mask;
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if (cpu_is_omap3517() || cpu_is_omap3505())
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mmc->slots[0].set_power = nop_mmc_set_power;
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else
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mmc->slots[0].features |= HSMMC_HAS_PBIAS;
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switch (c->mmc) {
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case 1:
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if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
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/* on-chip level shifting via PBIAS0/PBIAS1 */
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if (cpu_is_omap44xx()) {
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mmc->slots[0].before_set_reg =
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omap4_hsmmc1_before_set_reg;
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mmc->slots[0].after_set_reg =
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omap4_hsmmc1_after_set_reg;
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} else {
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mmc->slots[0].before_set_reg =
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omap_hsmmc1_before_set_reg;
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mmc->slots[0].after_set_reg =
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omap_hsmmc1_after_set_reg;
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}
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}
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/* Omap3630 HSMMC1 supports only 4-bit */
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if (cpu_is_omap3630() &&
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(c->caps & MMC_CAP_8_BIT_DATA)) {
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c->caps &= ~MMC_CAP_8_BIT_DATA;
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c->caps |= MMC_CAP_4_BIT_DATA;
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mmc->slots[0].caps = c->caps;
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}
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break;
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case 2:
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if (c->ext_clock)
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c->transceiver = 1;
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if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
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c->caps &= ~MMC_CAP_8_BIT_DATA;
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c->caps |= MMC_CAP_4_BIT_DATA;
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}
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/* FALLTHROUGH */
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case 3:
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if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
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/* off-chip level shifting, or none */
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mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
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mmc->slots[0].after_set_reg = NULL;
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}
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break;
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default:
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pr_err("MMC%d configuration not supported!\n", c->mmc);
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kfree(mmc);
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continue;
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}
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hsmmc_data[c->mmc - 1] = mmc;
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}
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omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
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/* pass the device nodes back to board setup code */
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for (c = controllers; c->mmc; c++) {
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struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
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if (!c->mmc || c->mmc > nr_hsmmc)
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continue;
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c->dev = mmc->dev;
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}
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done:
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for (i = 0; i < nr_hsmmc; i++)
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kfree(hsmmc_data[i]);
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}
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#endif
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