kernel-ark/arch/tile/lib
Chris Metcalf 2957c03539 tile: Provide atomic_{or,xor,and}
Implement atomic logic ops -- atomic_{or,xor,and}.

For tilegx, these are relatively straightforward; the architecture
provides atomic "or" and "and", both 32-bit and 64-bit.  To support
xor we provide a loop using "cmpexch".

For the older 32-bit tilepro architecture, we have to extend
the set of low-level assembly routines to include 32-bit "and",
as well as all three 64-bit routines.  Somewhat confusingly,
some 32-bit versions are already used by the bitops inlines, with
parameter types appropriate for bitops, so we have to do a bit of
casting to match "int" to "unsigned long".

Signed-off-by: Chris Metcalf <cmetcalf@ezchip.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1436474297-32187-1-git-send-email-cmetcalf@ezchip.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-27 14:06:24 +02:00
..
atomic_32.c tile: Provide atomic_{or,xor,and} 2015-07-27 14:06:24 +02:00
atomic_asm_32.S tile: Provide atomic_{or,xor,and} 2015-07-27 14:06:24 +02:00
cacheflush.c
checksum.c
cpumask.c
delay.c
exports.c tile: improve stack backtrace 2015-05-11 11:22:40 -04:00
Makefile
memchr_32.c
memchr_64.c
memcpy_32.S
memcpy_64.c
memcpy_user_64.c modpost: work correctly with tile coldtext sections 2015-07-08 18:53:49 -04:00
memmove.c
memset_32.c
memset_64.c
spinlock_32.c tile: modify arch_spin_unlock_wait() semantics 2015-04-28 22:43:13 -04:00
spinlock_64.c tile: modify arch_spin_unlock_wait() semantics 2015-04-28 22:43:13 -04:00
spinlock_common.h
strchr_32.c
strchr_64.c
string-endian.h
strlen_32.c
strlen_64.c
strnlen_32.c
strnlen_64.c
uaccess.c
usercopy_32.S tile: add <asm/word-at-a-time.h> and enable support functions 2015-04-30 15:23:37 -04:00
usercopy_64.S tile: add <asm/word-at-a-time.h> and enable support functions 2015-04-30 15:23:37 -04:00