35bdddb83f
Let the ieee1394 core select a suitable 1394 address range for sbp2's status FIFO instead of using a fixed range. Since the core only selects addresses which are guaranteed to be out of the "physical range" as per OHCI 1.1, this patch also fixes an old bug: OHCI controllers which implement a writeable PhysicalUpperBound register included sbp2's status FIFO in the physical range. That way sbp2 was never notified of a succesful login and always failed after timeout. Affected OHCI host adapters include ALi and Fujitsu controllers. As another side effect of this patch, the status FIFO is no longer located in a range for which OHCI chips perform "posted writes". Each status write now requires a response subaction. But since large data transfers involve only few status writes, there is no measurable decrease of I/O throughput. What's more, the status FIFO is now safe from potential host bus errors. Nevertheless, posted writes could be re-enabled by extensions to the ARM features of the 1394 stack. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de> Signed-off-by: Jody McIntyre <scjody@modernduck.com> (cherry picked from b2d38cccad4ef80d6b672b8f89aae5fe2907b113 commit) |
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| .. | ||
| .gitignore | ||
| config_roms.c | ||
| config_roms.h | ||
| csr1212.c | ||
| csr1212.h | ||
| csr.c | ||
| csr.h | ||
| dma.c | ||
| dma.h | ||
| dv1394-private.h | ||
| dv1394.c | ||
| dv1394.h | ||
| eth1394.c | ||
| eth1394.h | ||
| highlevel.c | ||
| highlevel.h | ||
| hosts.c | ||
| hosts.h | ||
| ieee1394_core.c | ||
| ieee1394_core.h | ||
| ieee1394_hotplug.h | ||
| ieee1394_transactions.c | ||
| ieee1394_transactions.h | ||
| ieee1394_types.h | ||
| ieee1394-ioctl.h | ||
| ieee1394.h | ||
| iso.c | ||
| iso.h | ||
| Kconfig | ||
| Makefile | ||
| nodemgr.c | ||
| nodemgr.h | ||
| ohci1394.c | ||
| ohci1394.h | ||
| oui2c.sh | ||
| oui.db | ||
| pcilynx.c | ||
| pcilynx.h | ||
| raw1394-private.h | ||
| raw1394.c | ||
| raw1394.h | ||
| sbp2.c | ||
| sbp2.h | ||
| video1394.c | ||
| video1394.h | ||