6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
68 lines
1.5 KiB
ArmAsm
68 lines
1.5 KiB
ArmAsm
/*
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* vDSO provided cache flush routines
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*
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* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
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* IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/vdso.h>
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#include <asm/asm-offsets.h>
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.text
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/*
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* Default "generic" version of __kernel_sync_dicache.
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*
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* void __kernel_sync_dicache(unsigned long start, unsigned long end)
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*
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* Flushes the data cache & invalidate the instruction cache for the
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* provided range [start, end[
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*
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* Note: all CPUs supported by this kernel have a 128 bytes cache
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* line size so we don't have to peek that info from the datapage
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*/
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V_FUNCTION_BEGIN(__kernel_sync_dicache)
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.cfi_startproc
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li r5,127
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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srwi. r8,r8,7 /* compute line count */
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crclr cr0*4+so
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beqlr /* nothing to do? */
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mtctr r8
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mr r3,r6
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1: dcbst 0,r3
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addi r3,r3,128
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bdnz 1b
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sync
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mtctr r8
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1: icbi 0,r6
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addi r6,r6,128
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bdnz 1b
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isync
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li r3,0
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blr
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.cfi_endproc
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V_FUNCTION_END(__kernel_sync_dicache)
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/*
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* POWER5 version of __kernel_sync_dicache
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*/
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V_FUNCTION_BEGIN(__kernel_sync_dicache_p5)
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.cfi_startproc
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crclr cr0*4+so
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sync
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isync
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li r3,0
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blr
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.cfi_endproc
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V_FUNCTION_END(__kernel_sync_dicache_p5)
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