cf0d19fb30
add simple-bus compatible property to soc nodes for 83xx/85xx platforms
that were missing them. Add same to platform probe code.
This fixes SoC device drivers (such as talitos) to succeed in matching
devices present in the soc node.
also update mpc836x_rdk dts to new SEC bindings (overlooked in commit
3fd4473: powerpc/fsl: update crypto node definition and device tree
instances).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
487 lines
12 KiB
Plaintext
487 lines
12 KiB
Plaintext
/*
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* MPC8548 CDS Device Tree Source
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*
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* Copyright 2006, 2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "MPC8548CDS";
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compatible = "MPC8548CDS", "MPC85xxCDS";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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/*
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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*/
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8548@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>; // 33 MHz, from uboot
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bus-frequency = <0>; // 166 MHz
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clock-frequency = <0>; // 825 MHz, from uboot
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x8000000>; // 128M at 0x0
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};
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soc8548@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x100000>;
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reg = <0xe0000000 0x1000>; // CCSRBAR
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bus-frequency = <0>;
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memory-controller@2000 {
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compatible = "fsl,8548-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,8548-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x80000>; // L2, 512K
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8548-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8548-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8548-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8548-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x24520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0x0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0x1>;
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device_type = "ethernet-phy";
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0x2>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0x3>;
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device_type = "ethernet-phy";
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};
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};
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enet0: ethernet@24000 {
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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};
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enet1: ethernet@25000 {
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 2 36 2 40 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy1>;
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};
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/* eTSEC 3/4 are currently broken
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enet2: ethernet@26000 {
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cell-index = <2>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <31 2 32 2 33 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy2>;
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};
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enet3: ethernet@27000 {
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cell-index = <3>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x27000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <37 2 38 2 39 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy3>;
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};
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*/
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { //global utilities reg
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compatible = "fsl,mpc8548-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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crypto@30000 {
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compatible = "fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <45 2>;
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interrupt-parent = <&mpic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0xfe>;
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fsl,descriptor-types-mask = <0x12b0ebf>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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};
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pci0: pci@e0008000 {
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cell-index = <0>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x4 (PCIX Slot 2) */
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0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
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0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
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0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
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0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x5 (PCIX Slot 3) */
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0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
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0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
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0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
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0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
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/* IDSEL 0x6 (PCIX Slot 4) */
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0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
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0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
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0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
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0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
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/* IDSEL 0x8 (PCIX Slot 5) */
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0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
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0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
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0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
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0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0xC (Tsi310 bridge) */
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0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
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0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
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0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
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0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x14 (Slot 2) */
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0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
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0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
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0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
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0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x15 (Slot 3) */
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0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
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0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
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0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
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0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
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/* IDSEL 0x16 (Slot 4) */
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0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
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0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
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0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
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0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
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/* IDSEL 0x18 (Slot 5) */
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0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
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0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
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0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
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0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
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0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
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0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
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0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
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0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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bus-range = <0 0>;
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ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008000 0x1000>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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pci_bridge@1c {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x00 (PrPMC Site) */
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0000 0x0 0x0 0x1 &mpic 0x0 0x1
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0000 0x0 0x0 0x2 &mpic 0x1 0x1
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0000 0x0 0x0 0x3 &mpic 0x2 0x1
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0000 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x04 (VIA chip) */
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0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
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0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
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0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
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0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x05 (8139) */
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0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
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/* IDSEL 0x06 (Slot 6) */
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0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
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0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
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0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
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0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
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/* IDESL 0x07 (Slot 7) */
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0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
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0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
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0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
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0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
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reg = <0xe000 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x80000>;
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clock-frequency = <33333333>;
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isa@4 {
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device_type = "isa";
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#interrupt-cells = <2>;
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <0x2000 0x0 0x0 0x0 0x0>;
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ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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interrupt-controller;
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device_type = "interrupt-controller";
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reg = <0x1 0x20 0x2
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0x1 0xa0 0x2
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0x1 0x4d0 0x2>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,iic";
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interrupts = <0 1>;
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interrupt-parent = <&mpic>;
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};
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rtc@70 {
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compatible = "pnpPNP,b00";
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reg = <0x1 0x70 0x2>;
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};
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};
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};
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};
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pci1: pci@e0009000 {
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cell-index = <1>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x15 */
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0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
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0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
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0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
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0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
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interrupt-parent = <&mpic>;
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interrupts = <25 2>;
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bus-range = <0 0>;
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ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
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0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0009000 0x1000>;
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compatible = "fsl,mpc8540-pci";
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device_type = "pci";
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};
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pci2: pcie@e000a000 {
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cell-index = <2>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0 (PEX) */
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00000 0x0 0x0 0x1 &mpic 0x0 0x1
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00000 0x0 0x0 0x2 &mpic 0x1 0x1
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00000 0x0 0x0 0x3 &mpic 0x2 0x1
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00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
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interrupt-parent = <&mpic>;
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interrupts = <26 2>;
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bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
|
|
0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
|
|
clock-frequency = <33333333>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xe000a000 0x1000>;
|
|
compatible = "fsl,mpc8548-pcie";
|
|
device_type = "pci";
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0xa0000000
|
|
0x2000000 0x0 0xa0000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x100000>;
|
|
};
|
|
};
|
|
};
|