c7e48e1e3e
Add add deepsleep for bf60x. 1. Call DMC init functions to enter and exit DDR self refresh mode. 2. Wait till CGU PLL is locked after wake up and exit DDR self refresh mode. 3. Make asessembly function enter_deepsleep comply with C funtion ABI in order to call other C functions. 4. Switch kernel stack by register EX_SCRATCH_REG. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
341 lines
10 KiB
C
341 lines
10 KiB
C
/*
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* Blackfin bf609 power management
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*
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* Copyright 2011 Analog Devices Inc.
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*
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* Licensed under the GPL-2
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*/
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#include <linux/suspend.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <asm/dpmc.h>
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#include <asm/pm.h>
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#include <mach/pm.h>
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#include <asm/blackfin.h>
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#include <asm/mem_init.h>
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/***********************************************************/
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/* */
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/* Wakeup Actions for DPM_RESTORE */
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/* */
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/***********************************************************/
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#define BITP_ROM_WUA_CHKHDR 24
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#define BITP_ROM_WUA_DDRLOCK 7
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#define BITP_ROM_WUA_DDRDLLEN 6
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#define BITP_ROM_WUA_DDR 5
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#define BITP_ROM_WUA_CGU 4
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#define BITP_ROM_WUA_MEMBOOT 2
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#define BITP_ROM_WUA_EN 1
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#define BITM_ROM_WUA_CHKHDR (0xFF000000)
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#define ENUM_ROM_WUA_CHKHDR_AD 0xAD000000
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#define BITM_ROM_WUA_DDRLOCK (0x00000080)
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#define BITM_ROM_WUA_DDRDLLEN (0x00000040)
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#define BITM_ROM_WUA_DDR (0x00000020)
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#define BITM_ROM_WUA_CGU (0x00000010)
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#define BITM_ROM_WUA_MEMBOOT (0x00000002)
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#define BITM_ROM_WUA_EN (0x00000001)
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/***********************************************************/
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/* */
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/* Syscontrol */
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/* */
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/***********************************************************/
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#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN 28 /* unlocks CGU_CTL register */
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#define BITP_ROM_SYSCTRL_WUA_OVERRIDE 24
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#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN 20 /* Saves the DDR DLL and PADS registers to the DPM registers */
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#define BITP_ROM_SYSCTRL_WUA_DDR 19 /* Saves the DDR registers to the DPM registers */
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#define BITP_ROM_SYSCTRL_WUA_CGU 18 /* Saves the CGU registers into DPM registers */
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#define BITP_ROM_SYSCTRL_WUA_DPMWRITE 17 /* Saves the Syscontrol structure structure contents into DPM registers */
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#define BITP_ROM_SYSCTRL_WUA_EN 16 /* reads current PLL and DDR configuration into structure */
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#define BITP_ROM_SYSCTRL_DDR_WRITE 13 /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */
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#define BITP_ROM_SYSCTRL_DDR_READ 12 /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */
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#define BITP_ROM_SYSCTRL_CGU_AUTODIS 11 /* Disables auto handling of UPDT and ALGN fields */
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#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL 7 /* access CGU_CLKOUTSEL register */
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#define BITP_ROM_SYSCTRL_CGU_DIV 6 /* access CGU_DIV register */
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#define BITP_ROM_SYSCTRL_CGU_STAT 5 /* access CGU_STAT register */
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#define BITP_ROM_SYSCTRL_CGU_CTL 4 /* access CGU_CTL register */
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#define BITP_ROM_SYSCTRL_CGU_RTNSTAT 2 /* Update structure STAT field upon error */
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#define BITP_ROM_SYSCTRL_WRITE 1 /* write registers */
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#define BITP_ROM_SYSCTRL_READ 0 /* read registers */
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#define BITM_ROM_SYSCTRL_CGU_READ (0x00000001) /* Read CGU registers */
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#define BITM_ROM_SYSCTRL_CGU_WRITE (0x00000002) /* Write registers */
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#define BITM_ROM_SYSCTRL_CGU_RTNSTAT (0x00000004) /* Update structure STAT field upon error or after a write operation */
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#define BITM_ROM_SYSCTRL_CGU_CTL (0x00000010) /* Access CGU_CTL register */
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#define BITM_ROM_SYSCTRL_CGU_STAT (0x00000020) /* Access CGU_STAT register */
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#define BITM_ROM_SYSCTRL_CGU_DIV (0x00000040) /* Access CGU_DIV register */
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#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL (0x00000080) /* Access CGU_CLKOUTSEL register */
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#define BITM_ROM_SYSCTRL_CGU_AUTODIS (0x00000800) /* Disables auto handling of UPDT and ALGN fields */
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#define BITM_ROM_SYSCTRL_DDR_READ (0x00001000) /* Reads the contents of the DDR registers and stores them into the structure */
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#define BITM_ROM_SYSCTRL_DDR_WRITE (0x00002000) /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */
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#define BITM_ROM_SYSCTRL_WUA_EN (0x00010000) /* Wakeup entry or exit opertation enable */
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#define BITM_ROM_SYSCTRL_WUA_DPMWRITE (0x00020000) /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */
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#define BITM_ROM_SYSCTRL_WUA_CGU (0x00040000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
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#define BITM_ROM_SYSCTRL_WUA_DDR (0x00080000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
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#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN (0x00100000) /* Enables saving/restoring of the DDR DLLCTL register */
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#define BITM_ROM_SYSCTRL_WUA_OVERRIDE (0x01000000)
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#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN (0x10000000) /* Unlocks the CGU_CTL register */
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/* Structures for the syscontrol() function */
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struct STRUCT_ROM_SYSCTRL {
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uint32_t ulCGU_CTL;
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uint32_t ulCGU_STAT;
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uint32_t ulCGU_DIV;
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uint32_t ulCGU_CLKOUTSEL;
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uint32_t ulWUA_Flags;
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uint32_t ulWUA_BootAddr;
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uint32_t ulWUA_User;
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uint32_t ulDDR_CTL;
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uint32_t ulDDR_CFG;
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uint32_t ulDDR_TR0;
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uint32_t ulDDR_TR1;
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uint32_t ulDDR_TR2;
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uint32_t ulDDR_MR;
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uint32_t ulDDR_EMR1;
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uint32_t ulDDR_EMR2;
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uint32_t ulDDR_PADCTL;
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uint32_t ulDDR_DLLCTL;
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uint32_t ulReserved;
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};
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struct bfin_pm_data {
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uint32_t magic;
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uint32_t resume_addr;
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uint32_t sp;
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};
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struct bfin_pm_data bf609_pm_data;
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struct STRUCT_ROM_SYSCTRL configvalues;
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uint32_t dactionflags;
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#define FUNC_ROM_SYSCONTROL 0xC8000080
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__attribute__((l1_data))
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static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL;
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__attribute__((l1_text))
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void bfin_cpu_suspend(void)
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{
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__asm__ __volatile__( \
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".align 8;" \
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"idle;" \
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: : \
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);
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}
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__attribute__((l1_text))
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void bf609_ddr_sr(void)
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{
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dmc_enter_self_refresh();
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}
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__attribute__((l1_text))
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void bf609_ddr_sr_exit(void)
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{
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dmc_exit_self_refresh();
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/* After wake up from deep sleep and exit DDR from self refress mode,
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* should wait till CGU PLL is locked.
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*/
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while (bfin_read32(CGU0_STAT) & CLKSALGN)
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continue;
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}
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__attribute__((l1_text))
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void bf609_resume_ccbuf(void)
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{
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bfin_write32(DPM0_CCBF_EN, 3);
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bfin_write32(DPM0_CTL, 2);
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while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
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}
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__attribute__((l1_text))
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void bfin_hibernate_syscontrol(void)
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{
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configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN
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| BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN);
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dactionflags = (BITM_ROM_SYSCTRL_WUA_EN
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| BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU
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| BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN);
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bfrom_SysControl(dactionflags, &configvalues, NULL);
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bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
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}
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#ifndef CONFIG_BF60x
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# define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
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#else
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# define SIC_SYSIRQ(irq) ((irq) - IVG15)
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#endif
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asmlinkage void enter_deepsleep(void);
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__attribute__((l1_text))
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void bfin_deepsleep(unsigned long mask)
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{
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bfin_write32(DPM0_WAKE_EN, 0x10);
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bfin_write32(DPM0_WAKE_POL, 0x10);
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SSYNC();
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enter_deepsleep();
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}
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void bfin_hibernate(unsigned long mask)
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{
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bfin_write32(DPM0_WAKE_EN, 0x10);
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bfin_write32(DPM0_WAKE_POL, 0x10);
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bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
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bfin_write32(DPM0_HIB_DIS, 0xFFFF);
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bf609_hibernate();
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}
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void bf609_cpu_pm_enter(suspend_state_t state)
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{
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int error;
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unsigned long wakeup = 0;
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unsigned long wakeup_pol = 0;
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#ifdef CONFIG_PM_BFIN_WAKE_PA15
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wakeup |= PA15WE;
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# if CONFIG_PM_BFIN_WAKE_PA15_POL
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wakeup_pol |= PA15WE;
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# endif
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_PB15
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wakeup |= PB15WE;
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# if CONFIG_PM_BFIN_WAKE_PA15_POL
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wakeup_pol |= PB15WE;
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# endif
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_PC15
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wakeup |= PC15WE;
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# if CONFIG_PM_BFIN_WAKE_PC15_POL
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wakeup_pol |= PC15WE;
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# endif
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_PD06
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wakeup |= PD06WE;
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# if CONFIG_PM_BFIN_WAKE_PD06_POL
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wakeup_pol |= PD06WE;
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# endif
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_PE12
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wakeup |= PE12WE;
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# if CONFIG_PM_BFIN_WAKE_PE12_POL
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wakeup_pol |= PE12WE;
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# endif
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_PG04
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wakeup |= PG04WE;
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# if CONFIG_PM_BFIN_WAKE_PG04_POL
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wakeup_pol |= PG04WE;
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# endif
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_PG13
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wakeup |= PG13WE;
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# if CONFIG_PM_BFIN_WAKE_PG13_POL
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wakeup_pol |= PG13WE;
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# endif
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_USB
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wakeup |= USBWE;
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# if CONFIG_PM_BFIN_WAKE_USB_POL
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wakeup_pol |= USBWE;
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# endif
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#endif
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error = irq_set_irq_wake(255, 1);
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if(error < 0)
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printk(KERN_DEBUG "Unable to get irq wake\n");
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error = irq_set_irq_wake(231, 1);
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if (error < 0)
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printk(KERN_DEBUG "Unable to get irq wake\n");
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if (state == PM_SUSPEND_STANDBY)
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bfin_deepsleep(wakeup);
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else {
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bfin_hibernate(wakeup);
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}
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}
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int bf609_cpu_pm_prepare(void)
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{
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return 0;
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}
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void bf609_cpu_pm_finish(void)
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{
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}
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static struct bfin_cpu_pm_fns bf609_cpu_pm = {
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.enter = bf609_cpu_pm_enter,
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.prepare = bf609_cpu_pm_prepare,
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.finish = bf609_cpu_pm_finish,
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};
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static irqreturn_t test_isr(int irq, void *dev_id)
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{
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printk(KERN_DEBUG "gpio irq %d\n", irq);
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return IRQ_HANDLED;
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}
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static irqreturn_t dpm0_isr(int irq, void *dev_id)
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{
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bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
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bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
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return IRQ_HANDLED;
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}
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#endif
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static int __init bf609_init_pm(void)
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{
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int irq;
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int error;
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#ifdef CONFIG_PM_BFIN_WAKE_PE12
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irq = gpio_to_irq(GPIO_PE12);
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if (irq < 0) {
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error = irq;
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printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n",
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GPIO_PE12, error);
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}
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error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL);
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if(error < 0)
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printk(KERN_DEBUG "Unable to get irq\n");
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#endif
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error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL);
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if(error < 0)
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printk(KERN_DEBUG "Unable to get irq\n");
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error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL);
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if (error < 0)
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printk(KERN_DEBUG "Unable to get irq\n");
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bfin_cpu_pm = &bf609_cpu_pm;
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return 0;
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}
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late_initcall(bf609_init_pm);
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