1469 lines
36 KiB
C
1469 lines
36 KiB
C
/*
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* Copyright (C) 2008-2009 MontaVista Software Inc.
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* Copyright (C) 2008-2009 Texas Instruments Inc
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*
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* Based on the LCD driver for TI Avalanche processors written by
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* Ajay Singh and Shalom Hai.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option)any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/fb.h>
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#include <linux/dma-mapping.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/uaccess.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/console.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/lcm.h>
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#include <video/da8xx-fb.h>
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#include <asm/div64.h>
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#define DRIVER_NAME "da8xx_lcdc"
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#define LCD_VERSION_1 1
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#define LCD_VERSION_2 2
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/* LCD Status Register */
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#define LCD_END_OF_FRAME1 BIT(9)
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#define LCD_END_OF_FRAME0 BIT(8)
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#define LCD_PL_LOAD_DONE BIT(6)
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#define LCD_FIFO_UNDERFLOW BIT(5)
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#define LCD_SYNC_LOST BIT(2)
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/* LCD DMA Control Register */
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#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
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#define LCD_DMA_BURST_1 0x0
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#define LCD_DMA_BURST_2 0x1
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#define LCD_DMA_BURST_4 0x2
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#define LCD_DMA_BURST_8 0x3
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#define LCD_DMA_BURST_16 0x4
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#define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
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#define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
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#define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
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#define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
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/* LCD Control Register */
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#define LCD_CLK_DIVISOR(x) ((x) << 8)
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#define LCD_RASTER_MODE 0x01
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/* LCD Raster Control Register */
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#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
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#define PALETTE_AND_DATA 0x00
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#define PALETTE_ONLY 0x01
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#define DATA_ONLY 0x02
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#define LCD_MONO_8BIT_MODE BIT(9)
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#define LCD_RASTER_ORDER BIT(8)
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#define LCD_TFT_MODE BIT(7)
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#define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
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#define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
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#define LCD_V1_PL_INT_ENA BIT(4)
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#define LCD_V2_PL_INT_ENA BIT(6)
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#define LCD_MONOCHROME_MODE BIT(1)
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#define LCD_RASTER_ENABLE BIT(0)
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#define LCD_TFT_ALT_ENABLE BIT(23)
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#define LCD_STN_565_ENABLE BIT(24)
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#define LCD_V2_DMA_CLK_EN BIT(2)
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#define LCD_V2_LIDD_CLK_EN BIT(1)
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#define LCD_V2_CORE_CLK_EN BIT(0)
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#define LCD_V2_LPP_B10 26
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/* LCD Raster Timing 2 Register */
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#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
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#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
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#define LCD_SYNC_CTRL BIT(25)
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#define LCD_SYNC_EDGE BIT(24)
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#define LCD_INVERT_PIXEL_CLOCK BIT(22)
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#define LCD_INVERT_LINE_CLOCK BIT(21)
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#define LCD_INVERT_FRAME_CLOCK BIT(20)
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/* LCD Block */
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#define LCD_PID_REG 0x0
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#define LCD_CTRL_REG 0x4
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#define LCD_STAT_REG 0x8
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#define LCD_RASTER_CTRL_REG 0x28
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#define LCD_RASTER_TIMING_0_REG 0x2C
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#define LCD_RASTER_TIMING_1_REG 0x30
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#define LCD_RASTER_TIMING_2_REG 0x34
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#define LCD_DMA_CTRL_REG 0x40
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#define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
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#define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
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#define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C
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#define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
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/* Interrupt Registers available only in Version 2 */
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#define LCD_RAW_STAT_REG 0x58
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#define LCD_MASKED_STAT_REG 0x5c
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#define LCD_INT_ENABLE_SET_REG 0x60
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#define LCD_INT_ENABLE_CLR_REG 0x64
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#define LCD_END_OF_INT_IND_REG 0x68
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/* Clock registers available only on Version 2 */
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#define LCD_CLK_ENABLE_REG 0x6c
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#define LCD_CLK_RESET_REG 0x70
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#define LCD_CLK_MAIN_RESET BIT(3)
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#define LCD_NUM_BUFFERS 2
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#define WSI_TIMEOUT 50
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#define PALETTE_SIZE 256
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#define LEFT_MARGIN 64
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#define RIGHT_MARGIN 64
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#define UPPER_MARGIN 32
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#define LOWER_MARGIN 32
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static resource_size_t da8xx_fb_reg_base;
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static struct resource *lcdc_regs;
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static unsigned int lcd_revision;
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static irq_handler_t lcdc_irq_handler;
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static inline unsigned int lcdc_read(unsigned int addr)
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{
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return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
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}
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static inline void lcdc_write(unsigned int val, unsigned int addr)
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{
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__raw_writel(val, da8xx_fb_reg_base + (addr));
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}
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struct da8xx_fb_par {
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resource_size_t p_palette_base;
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unsigned char *v_palette_base;
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dma_addr_t vram_phys;
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unsigned long vram_size;
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void *vram_virt;
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unsigned int dma_start;
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unsigned int dma_end;
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struct clk *lcdc_clk;
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int irq;
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unsigned short pseudo_palette[16];
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unsigned int palette_sz;
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unsigned int pxl_clk;
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int blank;
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wait_queue_head_t vsync_wait;
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int vsync_flag;
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int vsync_timeout;
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spinlock_t lock_for_chan_update;
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/*
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* LCDC has 2 ping pong DMA channels, channel 0
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* and channel 1.
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*/
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unsigned int which_dma_channel_done;
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#ifdef CONFIG_CPU_FREQ
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struct notifier_block freq_transition;
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unsigned int lcd_fck_rate;
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#endif
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void (*panel_power_ctrl)(int);
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};
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/* Variable Screen Information */
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static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
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.xoffset = 0,
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.yoffset = 0,
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.transp = {0, 0, 0},
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.nonstd = 0,
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.activate = 0,
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.height = -1,
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.width = -1,
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.accel_flags = 0,
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.left_margin = LEFT_MARGIN,
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.right_margin = RIGHT_MARGIN,
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.upper_margin = UPPER_MARGIN,
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.lower_margin = LOWER_MARGIN,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED
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};
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static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
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.id = "DA8xx FB Drv",
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.type = FB_TYPE_PACKED_PIXELS,
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.type_aux = 0,
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.visual = FB_VISUAL_PSEUDOCOLOR,
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.xpanstep = 0,
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.ypanstep = 1,
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.ywrapstep = 0,
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.accel = FB_ACCEL_NONE
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};
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struct da8xx_panel {
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const char name[25]; /* Full name <vendor>_<model> */
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unsigned short width;
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unsigned short height;
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int hfp; /* Horizontal front porch */
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int hbp; /* Horizontal back porch */
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int hsw; /* Horizontal Sync Pulse Width */
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int vfp; /* Vertical front porch */
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int vbp; /* Vertical back porch */
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int vsw; /* Vertical Sync Pulse Width */
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unsigned int pxl_clk; /* Pixel clock */
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unsigned char invert_pxl_clk; /* Invert Pixel clock */
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};
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static struct da8xx_panel known_lcd_panels[] = {
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/* Sharp LCD035Q3DG01 */
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[0] = {
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.name = "Sharp_LCD035Q3DG01",
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.width = 320,
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.height = 240,
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.hfp = 8,
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.hbp = 6,
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.hsw = 0,
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.vfp = 2,
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.vbp = 2,
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.vsw = 0,
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.pxl_clk = 4608000,
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.invert_pxl_clk = 1,
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},
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/* Sharp LK043T1DG01 */
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[1] = {
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.name = "Sharp_LK043T1DG01",
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.width = 480,
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.height = 272,
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.hfp = 2,
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.hbp = 2,
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.hsw = 41,
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.vfp = 2,
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.vbp = 2,
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.vsw = 10,
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.pxl_clk = 7833600,
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.invert_pxl_clk = 0,
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},
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[2] = {
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/* Hitachi SP10Q010 */
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.name = "SP10Q010",
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.width = 320,
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.height = 240,
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.hfp = 10,
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.hbp = 10,
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.hsw = 10,
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.vfp = 10,
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.vbp = 10,
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.vsw = 10,
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.pxl_clk = 7833600,
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.invert_pxl_clk = 0,
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},
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};
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/* Enable the Raster Engine of the LCD Controller */
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static inline void lcd_enable_raster(void)
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{
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u32 reg;
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/* Put LCDC in reset for several cycles */
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if (lcd_revision == LCD_VERSION_2)
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/* Write 1 to reset LCDC */
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lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
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mdelay(1);
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/* Bring LCDC out of reset */
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if (lcd_revision == LCD_VERSION_2)
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lcdc_write(0, LCD_CLK_RESET_REG);
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mdelay(1);
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/* Above reset sequence doesnot reset register context */
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reg = lcdc_read(LCD_RASTER_CTRL_REG);
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if (!(reg & LCD_RASTER_ENABLE))
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lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
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}
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/* Disable the Raster Engine of the LCD Controller */
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static inline void lcd_disable_raster(void)
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{
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u32 reg;
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reg = lcdc_read(LCD_RASTER_CTRL_REG);
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if (reg & LCD_RASTER_ENABLE)
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lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
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}
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static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
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{
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u32 start;
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u32 end;
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u32 reg_ras;
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u32 reg_dma;
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u32 reg_int;
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/* init reg to clear PLM (loading mode) fields */
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reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
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reg_ras &= ~(3 << 20);
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reg_dma = lcdc_read(LCD_DMA_CTRL_REG);
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if (load_mode == LOAD_DATA) {
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start = par->dma_start;
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end = par->dma_end;
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reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
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if (lcd_revision == LCD_VERSION_1) {
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reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
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} else {
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reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
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LCD_V2_END_OF_FRAME0_INT_ENA |
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LCD_V2_END_OF_FRAME1_INT_ENA;
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lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
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}
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reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
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lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
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lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
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lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
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lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
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} else if (load_mode == LOAD_PALETTE) {
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start = par->p_palette_base;
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end = start + par->palette_sz - 1;
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reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
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if (lcd_revision == LCD_VERSION_1) {
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reg_ras |= LCD_V1_PL_INT_ENA;
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} else {
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reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
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LCD_V2_PL_INT_ENA;
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lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
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}
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lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
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lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
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}
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lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
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lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
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/*
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* The Raster enable bit must be set after all other control fields are
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* set.
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*/
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lcd_enable_raster();
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}
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/* Configure the Burst Size and fifo threhold of DMA */
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static int lcd_cfg_dma(int burst_size, int fifo_th)
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{
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u32 reg;
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reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
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switch (burst_size) {
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case 1:
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reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
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break;
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case 2:
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reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
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break;
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case 4:
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reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
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break;
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case 8:
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reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
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break;
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case 16:
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reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
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break;
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default:
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return -EINVAL;
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}
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reg |= (fifo_th << 8);
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lcdc_write(reg, LCD_DMA_CTRL_REG);
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return 0;
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}
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static void lcd_cfg_ac_bias(int period, int transitions_per_int)
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{
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u32 reg;
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/* Set the AC Bias Period and Number of Transisitons per Interrupt */
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reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
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reg |= LCD_AC_BIAS_FREQUENCY(period) |
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LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
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lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
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}
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static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
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int front_porch)
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{
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u32 reg;
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reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
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reg |= ((back_porch & 0xff) << 24)
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| ((front_porch & 0xff) << 16)
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| ((pulse_width & 0x3f) << 10);
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lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
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}
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static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
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int front_porch)
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{
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u32 reg;
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reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
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reg |= ((back_porch & 0xff) << 24)
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| ((front_porch & 0xff) << 16)
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| ((pulse_width & 0x3f) << 10);
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lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
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}
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static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
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{
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u32 reg;
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u32 reg_int;
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reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
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LCD_MONO_8BIT_MODE |
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LCD_MONOCHROME_MODE);
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switch (cfg->p_disp_panel->panel_shade) {
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case MONOCHROME:
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reg |= LCD_MONOCHROME_MODE;
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if (cfg->mono_8bit_mode)
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reg |= LCD_MONO_8BIT_MODE;
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break;
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case COLOR_ACTIVE:
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reg |= LCD_TFT_MODE;
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if (cfg->tft_alt_mode)
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reg |= LCD_TFT_ALT_ENABLE;
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break;
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case COLOR_PASSIVE:
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if (cfg->stn_565_mode)
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reg |= LCD_STN_565_ENABLE;
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break;
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default:
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return -EINVAL;
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}
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/* enable additional interrupts here */
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if (lcd_revision == LCD_VERSION_1) {
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reg |= LCD_V1_UNDERFLOW_INT_ENA;
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} else {
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reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
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LCD_V2_UNDERFLOW_INT_ENA;
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lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
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}
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lcdc_write(reg, LCD_RASTER_CTRL_REG);
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reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
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if (cfg->sync_ctrl)
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reg |= LCD_SYNC_CTRL;
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else
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reg &= ~LCD_SYNC_CTRL;
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if (cfg->sync_edge)
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reg |= LCD_SYNC_EDGE;
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else
|
|
reg &= ~LCD_SYNC_EDGE;
|
|
|
|
if (cfg->invert_line_clock)
|
|
reg |= LCD_INVERT_LINE_CLOCK;
|
|
else
|
|
reg &= ~LCD_INVERT_LINE_CLOCK;
|
|
|
|
if (cfg->invert_frm_clock)
|
|
reg |= LCD_INVERT_FRAME_CLOCK;
|
|
else
|
|
reg &= ~LCD_INVERT_FRAME_CLOCK;
|
|
|
|
lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
|
|
u32 bpp, u32 raster_order)
|
|
{
|
|
u32 reg;
|
|
|
|
/* Set the Panel Width */
|
|
/* Pixels per line = (PPL + 1)*16 */
|
|
if (lcd_revision == LCD_VERSION_1) {
|
|
/*
|
|
* 0x3F in bits 4..9 gives max horizontal resolution = 1024
|
|
* pixels.
|
|
*/
|
|
width &= 0x3f0;
|
|
} else {
|
|
/*
|
|
* 0x7F in bits 4..10 gives max horizontal resolution = 2048
|
|
* pixels.
|
|
*/
|
|
width &= 0x7f0;
|
|
}
|
|
|
|
reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
|
|
reg &= 0xfffffc00;
|
|
if (lcd_revision == LCD_VERSION_1) {
|
|
reg |= ((width >> 4) - 1) << 4;
|
|
} else {
|
|
width = (width >> 4) - 1;
|
|
reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
|
|
}
|
|
lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
|
|
|
|
/* Set the Panel Height */
|
|
/* Set bits 9:0 of Lines Per Pixel */
|
|
reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
|
|
reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
|
|
lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
|
|
|
|
/* Set bit 10 of Lines Per Pixel */
|
|
if (lcd_revision == LCD_VERSION_2) {
|
|
reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
|
|
reg |= ((height - 1) & 0x400) << 16;
|
|
lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
|
|
}
|
|
|
|
/* Set the Raster Order of the Frame Buffer */
|
|
reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
|
|
if (raster_order)
|
|
reg |= LCD_RASTER_ORDER;
|
|
lcdc_write(reg, LCD_RASTER_CTRL_REG);
|
|
|
|
switch (bpp) {
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 16:
|
|
par->palette_sz = 16 * 2;
|
|
break;
|
|
|
|
case 8:
|
|
par->palette_sz = 256 * 2;
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
|
|
unsigned blue, unsigned transp,
|
|
struct fb_info *info)
|
|
{
|
|
struct da8xx_fb_par *par = info->par;
|
|
unsigned short *palette = (unsigned short *) par->v_palette_base;
|
|
u_short pal;
|
|
int update_hw = 0;
|
|
|
|
if (regno > 255)
|
|
return 1;
|
|
|
|
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
|
|
return 1;
|
|
|
|
if (info->var.bits_per_pixel == 4) {
|
|
if (regno > 15)
|
|
return 1;
|
|
|
|
if (info->var.grayscale) {
|
|
pal = regno;
|
|
} else {
|
|
red >>= 4;
|
|
green >>= 8;
|
|
blue >>= 12;
|
|
|
|
pal = (red & 0x0f00);
|
|
pal |= (green & 0x00f0);
|
|
pal |= (blue & 0x000f);
|
|
}
|
|
if (regno == 0)
|
|
pal |= 0x2000;
|
|
palette[regno] = pal;
|
|
|
|
} else if (info->var.bits_per_pixel == 8) {
|
|
red >>= 4;
|
|
green >>= 8;
|
|
blue >>= 12;
|
|
|
|
pal = (red & 0x0f00);
|
|
pal |= (green & 0x00f0);
|
|
pal |= (blue & 0x000f);
|
|
|
|
if (palette[regno] != pal) {
|
|
update_hw = 1;
|
|
palette[regno] = pal;
|
|
}
|
|
} else if ((info->var.bits_per_pixel == 16) && regno < 16) {
|
|
red >>= (16 - info->var.red.length);
|
|
red <<= info->var.red.offset;
|
|
|
|
green >>= (16 - info->var.green.length);
|
|
green <<= info->var.green.offset;
|
|
|
|
blue >>= (16 - info->var.blue.length);
|
|
blue <<= info->var.blue.offset;
|
|
|
|
par->pseudo_palette[regno] = red | green | blue;
|
|
|
|
if (palette[0] != 0x4000) {
|
|
update_hw = 1;
|
|
palette[0] = 0x4000;
|
|
}
|
|
}
|
|
|
|
/* Update the palette in the h/w as needed. */
|
|
if (update_hw)
|
|
lcd_blit(LOAD_PALETTE, par);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void lcd_reset(struct da8xx_fb_par *par)
|
|
{
|
|
/* Disable the Raster if previously Enabled */
|
|
lcd_disable_raster();
|
|
|
|
/* DMA has to be disabled */
|
|
lcdc_write(0, LCD_DMA_CTRL_REG);
|
|
lcdc_write(0, LCD_RASTER_CTRL_REG);
|
|
|
|
if (lcd_revision == LCD_VERSION_2) {
|
|
lcdc_write(0, LCD_INT_ENABLE_SET_REG);
|
|
/* Write 1 to reset */
|
|
lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
|
|
lcdc_write(0, LCD_CLK_RESET_REG);
|
|
}
|
|
}
|
|
|
|
static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
|
|
{
|
|
unsigned int lcd_clk, div;
|
|
|
|
lcd_clk = clk_get_rate(par->lcdc_clk);
|
|
div = lcd_clk / par->pxl_clk;
|
|
|
|
/* Configure the LCD clock divisor. */
|
|
lcdc_write(LCD_CLK_DIVISOR(div) |
|
|
(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
|
|
|
|
if (lcd_revision == LCD_VERSION_2)
|
|
lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
|
|
LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
|
|
|
|
}
|
|
|
|
static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
|
|
struct da8xx_panel *panel)
|
|
{
|
|
u32 bpp;
|
|
int ret = 0;
|
|
|
|
lcd_reset(par);
|
|
|
|
/* Calculate the divider */
|
|
lcd_calc_clk_divider(par);
|
|
|
|
if (panel->invert_pxl_clk)
|
|
lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
|
|
LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
|
|
else
|
|
lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
|
|
~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
|
|
|
|
/* Configure the DMA burst size and fifo threshold. */
|
|
ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Configure the AC bias properties. */
|
|
lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
|
|
|
|
/* Configure the vertical and horizontal sync properties. */
|
|
lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
|
|
lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
|
|
|
|
/* Configure for disply */
|
|
ret = lcd_cfg_display(cfg);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (QVGA != cfg->p_disp_panel->panel_type)
|
|
return -EINVAL;
|
|
|
|
if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
|
|
cfg->bpp >= cfg->p_disp_panel->min_bpp)
|
|
bpp = cfg->bpp;
|
|
else
|
|
bpp = cfg->p_disp_panel->max_bpp;
|
|
if (bpp == 12)
|
|
bpp = 16;
|
|
ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
|
|
(unsigned int)panel->height, bpp,
|
|
cfg->raster_order);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Configure FDD */
|
|
lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
|
|
(cfg->fdd << 12), LCD_RASTER_CTRL_REG);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* IRQ handler for version 2 of LCDC */
|
|
static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
|
|
{
|
|
struct da8xx_fb_par *par = arg;
|
|
u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
|
|
|
|
if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
|
|
lcd_disable_raster();
|
|
lcdc_write(stat, LCD_MASKED_STAT_REG);
|
|
lcd_enable_raster();
|
|
} else if (stat & LCD_PL_LOAD_DONE) {
|
|
/*
|
|
* Must disable raster before changing state of any control bit.
|
|
* And also must be disabled before clearing the PL loading
|
|
* interrupt via the following write to the status register. If
|
|
* this is done after then one gets multiple PL done interrupts.
|
|
*/
|
|
lcd_disable_raster();
|
|
|
|
lcdc_write(stat, LCD_MASKED_STAT_REG);
|
|
|
|
/* Disable PL completion interrupt */
|
|
lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
|
|
|
|
/* Setup and start data loading mode */
|
|
lcd_blit(LOAD_DATA, par);
|
|
} else {
|
|
lcdc_write(stat, LCD_MASKED_STAT_REG);
|
|
|
|
if (stat & LCD_END_OF_FRAME0) {
|
|
par->which_dma_channel_done = 0;
|
|
lcdc_write(par->dma_start,
|
|
LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
|
|
lcdc_write(par->dma_end,
|
|
LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
|
|
par->vsync_flag = 1;
|
|
wake_up_interruptible(&par->vsync_wait);
|
|
}
|
|
|
|
if (stat & LCD_END_OF_FRAME1) {
|
|
par->which_dma_channel_done = 1;
|
|
lcdc_write(par->dma_start,
|
|
LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
|
|
lcdc_write(par->dma_end,
|
|
LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
|
|
par->vsync_flag = 1;
|
|
wake_up_interruptible(&par->vsync_wait);
|
|
}
|
|
}
|
|
|
|
lcdc_write(0, LCD_END_OF_INT_IND_REG);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/* IRQ handler for version 1 LCDC */
|
|
static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
|
|
{
|
|
struct da8xx_fb_par *par = arg;
|
|
u32 stat = lcdc_read(LCD_STAT_REG);
|
|
u32 reg_ras;
|
|
|
|
if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
|
|
lcd_disable_raster();
|
|
lcdc_write(stat, LCD_STAT_REG);
|
|
lcd_enable_raster();
|
|
} else if (stat & LCD_PL_LOAD_DONE) {
|
|
/*
|
|
* Must disable raster before changing state of any control bit.
|
|
* And also must be disabled before clearing the PL loading
|
|
* interrupt via the following write to the status register. If
|
|
* this is done after then one gets multiple PL done interrupts.
|
|
*/
|
|
lcd_disable_raster();
|
|
|
|
lcdc_write(stat, LCD_STAT_REG);
|
|
|
|
/* Disable PL completion inerrupt */
|
|
reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
|
|
reg_ras &= ~LCD_V1_PL_INT_ENA;
|
|
lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
|
|
|
|
/* Setup and start data loading mode */
|
|
lcd_blit(LOAD_DATA, par);
|
|
} else {
|
|
lcdc_write(stat, LCD_STAT_REG);
|
|
|
|
if (stat & LCD_END_OF_FRAME0) {
|
|
par->which_dma_channel_done = 0;
|
|
lcdc_write(par->dma_start,
|
|
LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
|
|
lcdc_write(par->dma_end,
|
|
LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
|
|
par->vsync_flag = 1;
|
|
wake_up_interruptible(&par->vsync_wait);
|
|
}
|
|
|
|
if (stat & LCD_END_OF_FRAME1) {
|
|
par->which_dma_channel_done = 1;
|
|
lcdc_write(par->dma_start,
|
|
LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
|
|
lcdc_write(par->dma_end,
|
|
LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
|
|
par->vsync_flag = 1;
|
|
wake_up_interruptible(&par->vsync_wait);
|
|
}
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int fb_check_var(struct fb_var_screeninfo *var,
|
|
struct fb_info *info)
|
|
{
|
|
int err = 0;
|
|
|
|
switch (var->bits_per_pixel) {
|
|
case 1:
|
|
case 8:
|
|
var->red.offset = 0;
|
|
var->red.length = 8;
|
|
var->green.offset = 0;
|
|
var->green.length = 8;
|
|
var->blue.offset = 0;
|
|
var->blue.length = 8;
|
|
var->transp.offset = 0;
|
|
var->transp.length = 0;
|
|
var->nonstd = 0;
|
|
break;
|
|
case 4:
|
|
var->red.offset = 0;
|
|
var->red.length = 4;
|
|
var->green.offset = 0;
|
|
var->green.length = 4;
|
|
var->blue.offset = 0;
|
|
var->blue.length = 4;
|
|
var->transp.offset = 0;
|
|
var->transp.length = 0;
|
|
var->nonstd = FB_NONSTD_REV_PIX_IN_B;
|
|
break;
|
|
case 16: /* RGB 565 */
|
|
var->red.offset = 11;
|
|
var->red.length = 5;
|
|
var->green.offset = 5;
|
|
var->green.length = 6;
|
|
var->blue.offset = 0;
|
|
var->blue.length = 5;
|
|
var->transp.offset = 0;
|
|
var->transp.length = 0;
|
|
var->nonstd = 0;
|
|
break;
|
|
default:
|
|
err = -EINVAL;
|
|
}
|
|
|
|
var->red.msb_right = 0;
|
|
var->green.msb_right = 0;
|
|
var->blue.msb_right = 0;
|
|
var->transp.msb_right = 0;
|
|
return err;
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
|
|
unsigned long val, void *data)
|
|
{
|
|
struct da8xx_fb_par *par;
|
|
|
|
par = container_of(nb, struct da8xx_fb_par, freq_transition);
|
|
if (val == CPUFREQ_POSTCHANGE) {
|
|
if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
|
|
par->lcd_fck_rate = clk_get_rate(par->lcdc_clk);
|
|
lcd_disable_raster();
|
|
lcd_calc_clk_divider(par);
|
|
lcd_enable_raster();
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
|
|
{
|
|
par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
|
|
|
|
return cpufreq_register_notifier(&par->freq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
}
|
|
|
|
static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
|
|
{
|
|
cpufreq_unregister_notifier(&par->freq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
}
|
|
#endif
|
|
|
|
static int __devexit fb_remove(struct platform_device *dev)
|
|
{
|
|
struct fb_info *info = dev_get_drvdata(&dev->dev);
|
|
|
|
if (info) {
|
|
struct da8xx_fb_par *par = info->par;
|
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
lcd_da8xx_cpufreq_deregister(par);
|
|
#endif
|
|
if (par->panel_power_ctrl)
|
|
par->panel_power_ctrl(0);
|
|
|
|
lcd_disable_raster();
|
|
lcdc_write(0, LCD_RASTER_CTRL_REG);
|
|
|
|
/* disable DMA */
|
|
lcdc_write(0, LCD_DMA_CTRL_REG);
|
|
|
|
unregister_framebuffer(info);
|
|
fb_dealloc_cmap(&info->cmap);
|
|
dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
|
|
par->p_palette_base);
|
|
dma_free_coherent(NULL, par->vram_size, par->vram_virt,
|
|
par->vram_phys);
|
|
free_irq(par->irq, par);
|
|
clk_disable(par->lcdc_clk);
|
|
clk_put(par->lcdc_clk);
|
|
framebuffer_release(info);
|
|
iounmap((void __iomem *)da8xx_fb_reg_base);
|
|
release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
|
|
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Function to wait for vertical sync which for this LCD peripheral
|
|
* translates into waiting for the current raster frame to complete.
|
|
*/
|
|
static int fb_wait_for_vsync(struct fb_info *info)
|
|
{
|
|
struct da8xx_fb_par *par = info->par;
|
|
int ret;
|
|
|
|
/*
|
|
* Set flag to 0 and wait for isr to set to 1. It would seem there is a
|
|
* race condition here where the ISR could have occurred just before or
|
|
* just after this set. But since we are just coarsely waiting for
|
|
* a frame to complete then that's OK. i.e. if the frame completed
|
|
* just before this code executed then we have to wait another full
|
|
* frame time but there is no way to avoid such a situation. On the
|
|
* other hand if the frame completed just after then we don't need
|
|
* to wait long at all. Either way we are guaranteed to return to the
|
|
* user immediately after a frame completion which is all that is
|
|
* required.
|
|
*/
|
|
par->vsync_flag = 0;
|
|
ret = wait_event_interruptible_timeout(par->vsync_wait,
|
|
par->vsync_flag != 0,
|
|
par->vsync_timeout);
|
|
if (ret < 0)
|
|
return ret;
|
|
if (ret == 0)
|
|
return -ETIMEDOUT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fb_ioctl(struct fb_info *info, unsigned int cmd,
|
|
unsigned long arg)
|
|
{
|
|
struct lcd_sync_arg sync_arg;
|
|
|
|
switch (cmd) {
|
|
case FBIOGET_CONTRAST:
|
|
case FBIOPUT_CONTRAST:
|
|
case FBIGET_BRIGHTNESS:
|
|
case FBIPUT_BRIGHTNESS:
|
|
case FBIGET_COLOR:
|
|
case FBIPUT_COLOR:
|
|
return -ENOTTY;
|
|
case FBIPUT_HSYNC:
|
|
if (copy_from_user(&sync_arg, (char *)arg,
|
|
sizeof(struct lcd_sync_arg)))
|
|
return -EFAULT;
|
|
lcd_cfg_horizontal_sync(sync_arg.back_porch,
|
|
sync_arg.pulse_width,
|
|
sync_arg.front_porch);
|
|
break;
|
|
case FBIPUT_VSYNC:
|
|
if (copy_from_user(&sync_arg, (char *)arg,
|
|
sizeof(struct lcd_sync_arg)))
|
|
return -EFAULT;
|
|
lcd_cfg_vertical_sync(sync_arg.back_porch,
|
|
sync_arg.pulse_width,
|
|
sync_arg.front_porch);
|
|
break;
|
|
case FBIO_WAITFORVSYNC:
|
|
return fb_wait_for_vsync(info);
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int cfb_blank(int blank, struct fb_info *info)
|
|
{
|
|
struct da8xx_fb_par *par = info->par;
|
|
int ret = 0;
|
|
|
|
if (par->blank == blank)
|
|
return 0;
|
|
|
|
par->blank = blank;
|
|
switch (blank) {
|
|
case FB_BLANK_UNBLANK:
|
|
lcd_enable_raster();
|
|
|
|
if (par->panel_power_ctrl)
|
|
par->panel_power_ctrl(1);
|
|
break;
|
|
case FB_BLANK_NORMAL:
|
|
case FB_BLANK_VSYNC_SUSPEND:
|
|
case FB_BLANK_HSYNC_SUSPEND:
|
|
case FB_BLANK_POWERDOWN:
|
|
if (par->panel_power_ctrl)
|
|
par->panel_power_ctrl(0);
|
|
|
|
lcd_disable_raster();
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Set new x,y offsets in the virtual display for the visible area and switch
|
|
* to the new mode.
|
|
*/
|
|
static int da8xx_pan_display(struct fb_var_screeninfo *var,
|
|
struct fb_info *fbi)
|
|
{
|
|
int ret = 0;
|
|
struct fb_var_screeninfo new_var;
|
|
struct da8xx_fb_par *par = fbi->par;
|
|
struct fb_fix_screeninfo *fix = &fbi->fix;
|
|
unsigned int end;
|
|
unsigned int start;
|
|
unsigned long irq_flags;
|
|
|
|
if (var->xoffset != fbi->var.xoffset ||
|
|
var->yoffset != fbi->var.yoffset) {
|
|
memcpy(&new_var, &fbi->var, sizeof(new_var));
|
|
new_var.xoffset = var->xoffset;
|
|
new_var.yoffset = var->yoffset;
|
|
if (fb_check_var(&new_var, fbi))
|
|
ret = -EINVAL;
|
|
else {
|
|
memcpy(&fbi->var, &new_var, sizeof(new_var));
|
|
|
|
start = fix->smem_start +
|
|
new_var.yoffset * fix->line_length +
|
|
new_var.xoffset * fbi->var.bits_per_pixel / 8;
|
|
end = start + fbi->var.yres * fix->line_length - 1;
|
|
par->dma_start = start;
|
|
par->dma_end = end;
|
|
spin_lock_irqsave(&par->lock_for_chan_update,
|
|
irq_flags);
|
|
if (par->which_dma_channel_done == 0) {
|
|
lcdc_write(par->dma_start,
|
|
LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
|
|
lcdc_write(par->dma_end,
|
|
LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
|
|
} else if (par->which_dma_channel_done == 1) {
|
|
lcdc_write(par->dma_start,
|
|
LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
|
|
lcdc_write(par->dma_end,
|
|
LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
|
|
}
|
|
spin_unlock_irqrestore(&par->lock_for_chan_update,
|
|
irq_flags);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct fb_ops da8xx_fb_ops = {
|
|
.owner = THIS_MODULE,
|
|
.fb_check_var = fb_check_var,
|
|
.fb_setcolreg = fb_setcolreg,
|
|
.fb_pan_display = da8xx_pan_display,
|
|
.fb_ioctl = fb_ioctl,
|
|
.fb_fillrect = cfb_fillrect,
|
|
.fb_copyarea = cfb_copyarea,
|
|
.fb_imageblit = cfb_imageblit,
|
|
.fb_blank = cfb_blank,
|
|
};
|
|
|
|
/* Calculate and return pixel clock period in pico seconds */
|
|
static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par)
|
|
{
|
|
unsigned int lcd_clk, div;
|
|
unsigned int configured_pix_clk;
|
|
unsigned long long pix_clk_period_picosec = 1000000000000ULL;
|
|
|
|
lcd_clk = clk_get_rate(par->lcdc_clk);
|
|
div = lcd_clk / par->pxl_clk;
|
|
configured_pix_clk = (lcd_clk / div);
|
|
|
|
do_div(pix_clk_period_picosec, configured_pix_clk);
|
|
|
|
return pix_clk_period_picosec;
|
|
}
|
|
|
|
static int __devinit fb_probe(struct platform_device *device)
|
|
{
|
|
struct da8xx_lcdc_platform_data *fb_pdata =
|
|
device->dev.platform_data;
|
|
struct lcd_ctrl_config *lcd_cfg;
|
|
struct da8xx_panel *lcdc_info;
|
|
struct fb_info *da8xx_fb_info;
|
|
struct clk *fb_clk = NULL;
|
|
struct da8xx_fb_par *par;
|
|
resource_size_t len;
|
|
int ret, i;
|
|
unsigned long ulcm;
|
|
|
|
if (fb_pdata == NULL) {
|
|
dev_err(&device->dev, "Can not get platform data\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
|
|
if (!lcdc_regs) {
|
|
dev_err(&device->dev,
|
|
"Can not get memory resource for LCD controller\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
len = resource_size(lcdc_regs);
|
|
|
|
lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
|
|
if (!lcdc_regs)
|
|
return -EBUSY;
|
|
|
|
da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
|
|
if (!da8xx_fb_reg_base) {
|
|
ret = -EBUSY;
|
|
goto err_request_mem;
|
|
}
|
|
|
|
fb_clk = clk_get(&device->dev, NULL);
|
|
if (IS_ERR(fb_clk)) {
|
|
dev_err(&device->dev, "Can not get device clock\n");
|
|
ret = -ENODEV;
|
|
goto err_ioremap;
|
|
}
|
|
ret = clk_enable(fb_clk);
|
|
if (ret)
|
|
goto err_clk_put;
|
|
|
|
/* Determine LCD IP Version */
|
|
switch (lcdc_read(LCD_PID_REG)) {
|
|
case 0x4C100102:
|
|
lcd_revision = LCD_VERSION_1;
|
|
break;
|
|
case 0x4F200800:
|
|
lcd_revision = LCD_VERSION_2;
|
|
break;
|
|
default:
|
|
dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
|
|
"defaulting to LCD revision 1\n",
|
|
lcdc_read(LCD_PID_REG));
|
|
lcd_revision = LCD_VERSION_1;
|
|
break;
|
|
}
|
|
|
|
for (i = 0, lcdc_info = known_lcd_panels;
|
|
i < ARRAY_SIZE(known_lcd_panels);
|
|
i++, lcdc_info++) {
|
|
if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
|
|
break;
|
|
}
|
|
|
|
if (i == ARRAY_SIZE(known_lcd_panels)) {
|
|
dev_err(&device->dev, "GLCD: No valid panel found\n");
|
|
ret = -ENODEV;
|
|
goto err_clk_disable;
|
|
} else
|
|
dev_info(&device->dev, "GLCD: Found %s panel\n",
|
|
fb_pdata->type);
|
|
|
|
lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
|
|
|
|
da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
|
|
&device->dev);
|
|
if (!da8xx_fb_info) {
|
|
dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
|
|
ret = -ENOMEM;
|
|
goto err_clk_disable;
|
|
}
|
|
|
|
par = da8xx_fb_info->par;
|
|
par->lcdc_clk = fb_clk;
|
|
#ifdef CONFIG_CPU_FREQ
|
|
par->lcd_fck_rate = clk_get_rate(fb_clk);
|
|
#endif
|
|
par->pxl_clk = lcdc_info->pxl_clk;
|
|
if (fb_pdata->panel_power_ctrl) {
|
|
par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
|
|
par->panel_power_ctrl(1);
|
|
}
|
|
|
|
if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
|
|
dev_err(&device->dev, "lcd_init failed\n");
|
|
ret = -EFAULT;
|
|
goto err_release_fb;
|
|
}
|
|
|
|
/* allocate frame buffer */
|
|
par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
|
|
ulcm = lcm((lcdc_info->width * lcd_cfg->bpp)/8, PAGE_SIZE);
|
|
par->vram_size = roundup(par->vram_size/8, ulcm);
|
|
par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
|
|
|
|
par->vram_virt = dma_alloc_coherent(NULL,
|
|
par->vram_size,
|
|
(resource_size_t *) &par->vram_phys,
|
|
GFP_KERNEL | GFP_DMA);
|
|
if (!par->vram_virt) {
|
|
dev_err(&device->dev,
|
|
"GLCD: kmalloc for frame buffer failed\n");
|
|
ret = -EINVAL;
|
|
goto err_release_fb;
|
|
}
|
|
|
|
da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
|
|
da8xx_fb_fix.smem_start = par->vram_phys;
|
|
da8xx_fb_fix.smem_len = par->vram_size;
|
|
da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
|
|
|
|
par->dma_start = par->vram_phys;
|
|
par->dma_end = par->dma_start + lcdc_info->height *
|
|
da8xx_fb_fix.line_length - 1;
|
|
|
|
/* allocate palette buffer */
|
|
par->v_palette_base = dma_alloc_coherent(NULL,
|
|
PALETTE_SIZE,
|
|
(resource_size_t *)
|
|
&par->p_palette_base,
|
|
GFP_KERNEL | GFP_DMA);
|
|
if (!par->v_palette_base) {
|
|
dev_err(&device->dev,
|
|
"GLCD: kmalloc for palette buffer failed\n");
|
|
ret = -EINVAL;
|
|
goto err_release_fb_mem;
|
|
}
|
|
memset(par->v_palette_base, 0, PALETTE_SIZE);
|
|
|
|
par->irq = platform_get_irq(device, 0);
|
|
if (par->irq < 0) {
|
|
ret = -ENOENT;
|
|
goto err_release_pl_mem;
|
|
}
|
|
|
|
/* Initialize par */
|
|
da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
|
|
|
|
da8xx_fb_var.xres = lcdc_info->width;
|
|
da8xx_fb_var.xres_virtual = lcdc_info->width;
|
|
|
|
da8xx_fb_var.yres = lcdc_info->height;
|
|
da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
|
|
|
|
da8xx_fb_var.grayscale =
|
|
lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
|
|
da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
|
|
|
|
da8xx_fb_var.hsync_len = lcdc_info->hsw;
|
|
da8xx_fb_var.vsync_len = lcdc_info->vsw;
|
|
da8xx_fb_var.right_margin = lcdc_info->hfp;
|
|
da8xx_fb_var.left_margin = lcdc_info->hbp;
|
|
da8xx_fb_var.lower_margin = lcdc_info->vfp;
|
|
da8xx_fb_var.upper_margin = lcdc_info->vbp;
|
|
da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par);
|
|
|
|
/* Initialize fbinfo */
|
|
da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
|
|
da8xx_fb_info->fix = da8xx_fb_fix;
|
|
da8xx_fb_info->var = da8xx_fb_var;
|
|
da8xx_fb_info->fbops = &da8xx_fb_ops;
|
|
da8xx_fb_info->pseudo_palette = par->pseudo_palette;
|
|
da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
|
|
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
|
|
|
|
ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
|
|
if (ret)
|
|
goto err_release_pl_mem;
|
|
da8xx_fb_info->cmap.len = par->palette_sz;
|
|
|
|
/* initialize var_screeninfo */
|
|
da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
|
|
fb_set_var(da8xx_fb_info, &da8xx_fb_var);
|
|
|
|
dev_set_drvdata(&device->dev, da8xx_fb_info);
|
|
|
|
/* initialize the vsync wait queue */
|
|
init_waitqueue_head(&par->vsync_wait);
|
|
par->vsync_timeout = HZ / 5;
|
|
par->which_dma_channel_done = -1;
|
|
spin_lock_init(&par->lock_for_chan_update);
|
|
|
|
/* Register the Frame Buffer */
|
|
if (register_framebuffer(da8xx_fb_info) < 0) {
|
|
dev_err(&device->dev,
|
|
"GLCD: Frame Buffer Registration Failed!\n");
|
|
ret = -EINVAL;
|
|
goto err_dealloc_cmap;
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
ret = lcd_da8xx_cpufreq_register(par);
|
|
if (ret) {
|
|
dev_err(&device->dev, "failed to register cpufreq\n");
|
|
goto err_cpu_freq;
|
|
}
|
|
#endif
|
|
|
|
if (lcd_revision == LCD_VERSION_1)
|
|
lcdc_irq_handler = lcdc_irq_handler_rev01;
|
|
else
|
|
lcdc_irq_handler = lcdc_irq_handler_rev02;
|
|
|
|
ret = request_irq(par->irq, lcdc_irq_handler, 0,
|
|
DRIVER_NAME, par);
|
|
if (ret)
|
|
goto irq_freq;
|
|
return 0;
|
|
|
|
irq_freq:
|
|
#ifdef CONFIG_CPU_FREQ
|
|
lcd_da8xx_cpufreq_deregister(par);
|
|
err_cpu_freq:
|
|
#endif
|
|
unregister_framebuffer(da8xx_fb_info);
|
|
|
|
err_dealloc_cmap:
|
|
fb_dealloc_cmap(&da8xx_fb_info->cmap);
|
|
|
|
err_release_pl_mem:
|
|
dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
|
|
par->p_palette_base);
|
|
|
|
err_release_fb_mem:
|
|
dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
|
|
|
|
err_release_fb:
|
|
framebuffer_release(da8xx_fb_info);
|
|
|
|
err_clk_disable:
|
|
clk_disable(fb_clk);
|
|
|
|
err_clk_put:
|
|
clk_put(fb_clk);
|
|
|
|
err_ioremap:
|
|
iounmap((void __iomem *)da8xx_fb_reg_base);
|
|
|
|
err_request_mem:
|
|
release_mem_region(lcdc_regs->start, len);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int fb_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
struct fb_info *info = platform_get_drvdata(dev);
|
|
struct da8xx_fb_par *par = info->par;
|
|
|
|
console_lock();
|
|
if (par->panel_power_ctrl)
|
|
par->panel_power_ctrl(0);
|
|
|
|
fb_set_suspend(info, 1);
|
|
lcd_disable_raster();
|
|
clk_disable(par->lcdc_clk);
|
|
console_unlock();
|
|
|
|
return 0;
|
|
}
|
|
static int fb_resume(struct platform_device *dev)
|
|
{
|
|
struct fb_info *info = platform_get_drvdata(dev);
|
|
struct da8xx_fb_par *par = info->par;
|
|
|
|
console_lock();
|
|
clk_enable(par->lcdc_clk);
|
|
lcd_enable_raster();
|
|
|
|
if (par->panel_power_ctrl)
|
|
par->panel_power_ctrl(1);
|
|
|
|
fb_set_suspend(info, 0);
|
|
console_unlock();
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
#define fb_suspend NULL
|
|
#define fb_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver da8xx_fb_driver = {
|
|
.probe = fb_probe,
|
|
.remove = __devexit_p(fb_remove),
|
|
.suspend = fb_suspend,
|
|
.resume = fb_resume,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init da8xx_fb_init(void)
|
|
{
|
|
return platform_driver_register(&da8xx_fb_driver);
|
|
}
|
|
|
|
static void __exit da8xx_fb_cleanup(void)
|
|
{
|
|
platform_driver_unregister(&da8xx_fb_driver);
|
|
}
|
|
|
|
module_init(da8xx_fb_init);
|
|
module_exit(da8xx_fb_cleanup);
|
|
|
|
MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
|
|
MODULE_AUTHOR("Texas Instruments");
|
|
MODULE_LICENSE("GPL");
|