c8d86be387
This is a driver for the Realtek 8187 "SE" wireless PCI devices in some netbook computers (MSI Wind, and others). It includes its own copy of the ieee80211 stack, but it is compiled into the driver to prevend duplicate symbol issues. This version comes from Ralink with no authorship, but it is based on an old version of the rtl8180 driver from Andrea Merello. It was hacked up a bit to get it to build properly within the kernel tree and to properly handle the merged wireless stack within the driver. Cc: Andrea Merello <andreamrl@tiscali.it> Cc: linux-wireless <linux-wireless@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
234 lines
5.3 KiB
C
234 lines
5.3 KiB
C
/*
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This files contains PHILIPS SA2400 radio frontend programming routines.
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This is part of rtl8180 OpenSource driver
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Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
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Released under the terms of GPL (General Public Licence)
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Parts of this driver are based on the GPL part of the
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official realtek driver
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Parts of this driver are based on the rtl8180 driver skeleton
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from Patric Schenke & Andres Salomon
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Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
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Code at http://che.ojctech.com/~dyoung/rtw/ has been useful to me to
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understand some things.
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Code from rtl8181 project has been useful to me to understand some things.
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We want to tanks the Authors of such projects and the Ndiswrapper
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project Authors.
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*/
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#include "r8180.h"
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#include "r8180_hw.h"
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#include "r8180_sa2400.h"
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//#define DEBUG_SA2400
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u32 sa2400_chan[] = {
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0x0, //dummy channel 0
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0x00096c, //1
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0x080970, //2
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0x100974, //3
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0x180978, //4
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0x000980, //5
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0x080984, //6
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0x100988, //7
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0x18098c, //8
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0x000994, //9
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0x080998, //10
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0x10099c, //11
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0x1809a0, //12
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0x0009a8, //13
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0x0009b4, //14
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};
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void rf_stabilize(struct net_device *dev)
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{
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force_pci_posting(dev);
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mdelay(3); //for now use a great value.. we may optimize in future
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}
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void write_sa2400(struct net_device *dev,u8 adr, u32 data)
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{
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// struct r8180_priv *priv = ieee80211_priv(dev);
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u32 phy_config;
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// philips sa2400 expects 24 bits data
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/*if(adr == 4 && priv->digphy){
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phy_config=0x60000000;
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}else{
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phy_config=0xb0000000;
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}*/
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phy_config = 0xb0000000; // MAC will bang bits to the sa2400
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phy_config |= (((u32)(adr&0xf))<< 24);
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phy_config |= (data & 0xffffff);
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write_nic_dword(dev,PHY_CONFIG,phy_config);
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#ifdef DEBUG_SA2400
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DMESG("Writing sa2400: %x (adr %x)",phy_config,adr);
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#endif
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rf_stabilize(dev);
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}
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void sa2400_write_phy_antenna(struct net_device *dev,short ch)
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{
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struct r8180_priv *priv = ieee80211_priv(dev);
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u8 ant;
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ant = SA2400_ANTENNA;
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if(priv->antb) /*default antenna is antenna B */
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ant |= BB_ANTENNA_B;
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if(ch == 14)
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ant |= BB_ANTATTEN_CHAN14;
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write_phy(dev,0x10,ant);
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//DMESG("BB antenna %x ",ant);
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}
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/* from the rtl8181 embedded driver */
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short sa2400_rf_set_sens(struct net_device *dev, short sens)
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{
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u8 finetune = 0;
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if ((sens > 85) || (sens < 54)) return -1;
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write_sa2400(dev,5,0x1dfb | (sens-54) << 15 |(finetune<<20)); // AGC 0xc9dfb
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return 0;
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}
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void sa2400_rf_set_chan(struct net_device *dev, short ch)
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{
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struct r8180_priv *priv = ieee80211_priv(dev);
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u32 txpw = 0xff & priv->chtxpwr[ch];
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u32 chan = sa2400_chan[ch];
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write_sa2400(dev,7,txpw);
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//write_phy(dev,0x10,0xd1);
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sa2400_write_phy_antenna(dev,ch);
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write_sa2400(dev,0,chan);
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write_sa2400(dev,1,0xbb50);
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write_sa2400(dev,2,0x80);
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write_sa2400(dev,3,0);
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}
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void sa2400_rf_close(struct net_device *dev)
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{
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write_sa2400(dev, 4, 0);
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}
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void sa2400_rf_init(struct net_device *dev)
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{
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struct r8180_priv *priv = ieee80211_priv(dev);
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u32 anaparam;
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u8 firdac;
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write_nic_byte(dev,PHY_DELAY,0x6); //this is general
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write_nic_byte(dev,CARRIER_SENSE_COUNTER,0x4c); //this is general
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/*these are philips sa2400 specific*/
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anaparam = read_nic_dword(dev,ANAPARAM);
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anaparam = anaparam &~ (1<<ANAPARAM_TXDACOFF_SHIFT);
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anaparam = anaparam &~ANAPARAM_PWR1_MASK;
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anaparam = anaparam &~ANAPARAM_PWR0_MASK;
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if(priv->digphy){
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anaparam |= (SA2400_DIG_ANAPARAM_PWR1_ON<<ANAPARAM_PWR1_SHIFT);
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anaparam |= (SA2400_ANAPARAM_PWR0_ON<<ANAPARAM_PWR0_SHIFT);
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}else{
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anaparam |= (SA2400_ANA_ANAPARAM_PWR1_ON<<ANAPARAM_PWR1_SHIFT);
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}
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rtl8180_set_anaparam(dev,anaparam);
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firdac = (priv->digphy) ? (1<<SA2400_REG4_FIRDAC_SHIFT) : 0;
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write_sa2400(dev,0,sa2400_chan[priv->chan]);
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write_sa2400(dev,1,0xbb50);
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write_sa2400(dev,2,0x80);
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write_sa2400(dev,3,0);
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write_sa2400(dev,4,0x19340 | firdac);
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write_sa2400(dev,5,0xc9dfb); // AGC
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write_sa2400(dev,4,0x19348 | firdac); //calibrates VCO
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if(priv->digphy)
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write_sa2400(dev,4,0x1938c); /*???*/
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write_sa2400(dev,4,0x19340 | firdac);
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write_sa2400(dev,0,sa2400_chan[priv->chan]);
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write_sa2400(dev,1,0xbb50);
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write_sa2400(dev,2,0x80);
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write_sa2400(dev,3,0);
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write_sa2400(dev,4,0x19344 | firdac); //calibrates filter
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/* new from rtl8180 embedded driver (rtl8181 project) */
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write_sa2400(dev,6,0x13ff | (1<<23)); // MANRX
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write_sa2400(dev,8,0); //VCO
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if(!priv->digphy)
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{
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rtl8180_set_anaparam(dev, anaparam | \
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(1<<ANAPARAM_TXDACOFF_SHIFT));
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rtl8180_conttx_enable(dev);
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write_sa2400(dev, 4, 0x19341); // calibrates DC
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/* a 5us sleep is required here,
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we rely on the 3ms delay introduced in write_sa2400
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*/
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write_sa2400(dev, 4, 0x19345);
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/* a 20us sleep is required here,
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we rely on the 3ms delay introduced in write_sa2400
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*/
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rtl8180_conttx_disable(dev);
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rtl8180_set_anaparam(dev, anaparam);
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}
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/* end new */
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write_sa2400(dev,4,0x19341 | firdac ); //RTX MODE
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// Set tx power level !?
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/*baseband configuration*/
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write_phy(dev,0,0x98);
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write_phy(dev,3,0x38);
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write_phy(dev,4,0xe0);
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write_phy(dev,5,0x90);
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write_phy(dev,6,0x1a);
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write_phy(dev,7,0x64);
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/*Should be done something more here??*/
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sa2400_write_phy_antenna(dev,priv->chan);
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write_phy(dev,0x11,0x80);
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if(priv->diversity)
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write_phy(dev,0x12,0xc7);
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else
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write_phy(dev,0x12,0x47);
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write_phy(dev,0x13,0x90 | priv->cs_treshold );
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write_phy(dev,0x19,0x0);
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write_phy(dev,0x1a,0xa0);
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sa2400_rf_set_chan(dev,priv->chan);
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}
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