afe4b25e7d
XScale cores either have a DSP coprocessor (which contains a single 40 bit accumulator register), or an iWMMXt coprocessor (which contains eight 64 bit registers.) Because of the small amount of state in the DSP coprocessor, access to the DSP coprocessor (CP0) is always enabled, and DSP context switching is done unconditionally on every task switch. Access to the iWMMXt coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is first issued, and iWMMXt context switching is done lazily. CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will have iWMMXt support', but boards are supposed to select this config symbol by hand, and at least one pxa27x board doesn't get this right, so on that board, proc-xscale.S will incorrectly assume that we have a DSP coprocessor, enable CP0 on boot, and we will then only save the first iWMMXt register (wR0) on context switches, which is Bad. This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on might have iWMMXt support, and we will enable iWMMXt context switching if it does.' This means that with this patch, running a CONFIG_IWMMXT=n kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt state over context switches, and running a CONFIG_IWMMXT=y kernel on a non-iWMMXt capable CPU will still do DSP context save/restore. These changes should make iWMMXt work on PXA3xx, and as a side effect, enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined), as well as setting and using HWCAP_IWMMXT properly. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
139 lines
3.8 KiB
C
139 lines
3.8 KiB
C
#ifndef __ASMARM_ELF_H
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#define __ASMARM_ELF_H
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#ifndef __ASSEMBLY__
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/*
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* ELF register definitions..
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*/
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#include <asm/ptrace.h>
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#include <asm/user.h>
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typedef unsigned long elf_greg_t;
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typedef unsigned long elf_freg_t[3];
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#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
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typedef elf_greg_t elf_gregset_t[ELF_NGREG];
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typedef struct user_fp elf_fpregset_t;
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#endif
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#define EM_ARM 40
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#define EF_ARM_APCS26 0x08
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#define EF_ARM_SOFT_FLOAT 0x200
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#define EF_ARM_EABI_MASK 0xFF000000
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#define R_ARM_NONE 0
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#define R_ARM_PC24 1
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#define R_ARM_ABS32 2
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#define R_ARM_CALL 28
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#define R_ARM_JUMP24 29
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/*
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* These are used to set parameters in the core dumps.
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*/
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#define ELF_CLASS ELFCLASS32
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#ifdef __ARMEB__
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#define ELF_DATA ELFDATA2MSB
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#else
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#define ELF_DATA ELFDATA2LSB
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#endif
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#define ELF_ARCH EM_ARM
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/*
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* HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
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*/
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#define HWCAP_SWP 1
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#define HWCAP_HALF 2
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#define HWCAP_THUMB 4
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#define HWCAP_26BIT 8 /* Play it safe */
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#define HWCAP_FAST_MULT 16
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#define HWCAP_FPA 32
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#define HWCAP_VFP 64
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#define HWCAP_EDSP 128
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#define HWCAP_JAVA 256
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#define HWCAP_IWMMXT 512
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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/*
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* This yields a mask that user programs can use to figure out what
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* instruction set this cpu supports.
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*/
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#define ELF_HWCAP (elf_hwcap)
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extern unsigned int elf_hwcap;
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/*
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* This yields a string that ld.so will use to load implementation
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* specific libraries for optimization. This is more specific in
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* intent than poking at uname or /proc/cpuinfo.
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*
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* For now we just provide a fairly general string that describes the
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* processor family. This could be made more specific later if someone
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* implemented optimisations that require it. 26-bit CPUs give you
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* "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't
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* supported). 32-bit CPUs give you "v3[lb]" for anything based on an
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* ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1
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* core.
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*/
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#define ELF_PLATFORM_SIZE 8
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#define ELF_PLATFORM (elf_platform)
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extern char elf_platform[];
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#endif
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/*
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* This is used to ensure we don't load something for the wrong architecture.
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*/
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#define elf_check_arch(x) ((x)->e_machine == EM_ARM && ELF_PROC_OK(x))
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/*
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* 32-bit code is always OK. Some cpus can do 26-bit, some can't.
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*/
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#define ELF_PROC_OK(x) (ELF_THUMB_OK(x) && ELF_26BIT_OK(x))
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#define ELF_THUMB_OK(x) \
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((elf_hwcap & HWCAP_THUMB && ((x)->e_entry & 1) == 1) || \
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((x)->e_entry & 3) == 0)
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#define ELF_26BIT_OK(x) \
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((elf_hwcap & HWCAP_26BIT && (x)->e_flags & EF_ARM_APCS26) || \
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((x)->e_flags & EF_ARM_APCS26) == 0)
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#define USE_ELF_CORE_DUMP
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#define ELF_EXEC_PAGESIZE 4096
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/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
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use of this is to invoke "./ld.so someprog" to test out a new version of
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the loader. We need to make sure that it is out of the way of the program
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that it will "exec", and that there is sufficient room for the brk. */
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#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
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/* When the program starts, a1 contains a pointer to a function to be
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registered with atexit, as per the SVR4 ABI. A value of 0 means we
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have no such handler. */
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#define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0
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/*
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* Since the FPA coprocessor uses CP1 and CP2, and iWMMXt uses CP0
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* and CP1, we only enable access to the iWMMXt coprocessor if the
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* binary is EABI or softfloat (and thus, guaranteed not to use
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* FPA instructions.)
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*/
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#define SET_PERSONALITY(ex, ibcs2) \
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do { \
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if ((ex).e_flags & EF_ARM_APCS26) { \
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set_personality(PER_LINUX); \
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} else { \
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set_personality(PER_LINUX_32BIT); \
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if (elf_hwcap & HWCAP_IWMMXT && (ex).e_flags & (EF_ARM_EABI_MASK | EF_ARM_SOFT_FLOAT)) \
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set_thread_flag(TIF_USING_IWMMXT); \
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else \
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clear_thread_flag(TIF_USING_IWMMXT); \
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} \
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} while (0)
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#endif
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#endif
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