bbe963f1b9
This moves dcon_source and dcon_pending into the dcon_priv struct. Because these variables are used by the IRQ handler (which is registered in the model-specific callbacks), we end up needing to move dcon_priv into olpc_dcon.h. This also changes the IRQ registration to use the dcon_priv pointer as dev_id, instead of dcon_driver. Signed-off-by: Andres Salomon <dilinger@queued.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
193 lines
4.6 KiB
C
193 lines
4.6 KiB
C
/*
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* Copyright (c) 2009,2010 One Laptop per Child
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*
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* This program is free software. You can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General Public
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* License as published by the Free Software Foundation.
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*/
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#include <linux/acpi.h>
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#include <linux/pci.h>
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#include <linux/gpio.h>
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#include <asm/olpc.h>
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/* TODO: this eventually belongs in linux/vx855.h */
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#define NR_VX855_GPI 14
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#define NR_VX855_GPO 13
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#define NR_VX855_GPIO 15
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#define VX855_GPI(n) (n)
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#define VX855_GPO(n) (NR_VX855_GPI + (n))
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#define VX855_GPIO(n) (NR_VX855_GPI + NR_VX855_GPO + (n))
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#include "olpc_dcon.h"
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/* Hardware setup on the XO 1.5:
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* DCONLOAD connects to
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* VX855_GPIO1 (not SMBCK2)
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* DCONBLANK connects to VX855_GPIO8 (not SSPICLK) unused in driver
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* DCONSTAT0 connects to VX855_GPI10 (not SSPISDI)
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* DCONSTAT1 connects to VX855_GPI11 (not nSSPISS)
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* DCONIRQ connects to VX855_GPIO12
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* DCONSMBDATA connects to VX855 graphics CRTSPD
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* DCONSMBCLK connects to VX855 graphics CRTSPCLK
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*/
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#define VX855_GENL_PURPOSE_OUTPUT 0x44c // PMIO_Rx4c-4f
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#define VX855_GPI_STATUS_CHG 0x450 // PMIO_Rx50
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#define VX855_GPI_SCI_SMI 0x452 // PMIO_Rx52
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#define BIT_GPIO12 0x40
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#define PREFIX "OLPC DCON:"
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static void dcon_clear_irq(void)
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{
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/* irq status will appear in PMIO_Rx50[6] (RW1C) on gpio12 */
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outb(BIT_GPIO12, VX855_GPI_STATUS_CHG);
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}
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static int dcon_was_irq(void)
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{
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u_int8_t tmp;
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/* irq status will appear in PMIO_Rx50[6] on gpio12 */
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tmp = inb(VX855_GPI_STATUS_CHG);
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return !!(tmp & BIT_GPIO12);
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return 0;
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}
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static int dcon_init_xo_1_5(struct dcon_priv *dcon)
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{
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unsigned int irq;
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u_int8_t tmp;
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struct pci_dev *pdev;
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pdev = pci_get_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VX855, NULL);
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if (!pdev) {
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printk(KERN_ERR "cannot find VX855 PCI ID\n");
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return 1;
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}
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pci_read_config_byte(pdev, 0x95, &tmp);
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pci_write_config_byte(pdev, 0x95, tmp|0x0c);
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/* Set GPIO8 to GPIO mode, not SSPICLK */
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pci_read_config_byte(pdev, 0xe3, &tmp);
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pci_write_config_byte(pdev, 0xe3, tmp | 0x04);
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/* Set GPI10/GPI11 to GPI mode, not SSPISDI/SSPISS */
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pci_read_config_byte(pdev, 0xe4, &tmp);
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pci_write_config_byte(pdev, 0xe4, tmp|0x08);
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/* clear PMU_RxE1[6] to select SCI on GPIO12 */
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/* clear PMU_RxE0[6] to choose falling edge */
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pci_read_config_byte(pdev, 0xe1, &tmp);
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pci_write_config_byte(pdev, 0xe1, tmp & ~BIT_GPIO12);
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pci_read_config_byte(pdev, 0xe0, &tmp);
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pci_write_config_byte(pdev, 0xe0, tmp & ~BIT_GPIO12);
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dcon_clear_irq();
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/* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
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outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
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/* Determine the current state of DCONLOAD, likely set by firmware */
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/* GPIO1 */
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dcon->curr_src = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ?
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DCON_SOURCE_CPU : DCON_SOURCE_DCON;
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dcon->pending_src = dcon->curr_src;
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pci_dev_put(pdev);
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/* we're sharing the IRQ with ACPI */
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irq = acpi_gbl_FADT.sci_interrupt;
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if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", dcon)) {
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printk(KERN_ERR PREFIX "DCON (IRQ%d) allocation failed\n", irq);
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return 1;
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}
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return 0;
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}
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static void set_i2c_line(int sda, int scl)
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{
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unsigned char tmp;
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unsigned int port = 0x26;
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/* FIXME: This directly accesses the CRT GPIO controller !!! */
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outb(port, 0x3c4);
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tmp = inb(0x3c5);
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if (scl)
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tmp |= 0x20;
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else
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tmp &= ~0x20;
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if (sda)
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tmp |= 0x10;
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else
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tmp &= ~0x10;
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tmp |= 0x01;
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outb(port, 0x3c4);
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outb(tmp, 0x3c5);
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}
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static void dcon_wiggle_xo_1_5(void)
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{
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int x;
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/*
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* According to HiMax, when powering the DCON up we should hold
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* SMB_DATA high for 8 SMB_CLK cycles. This will force the DCON
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* state machine to reset to a (sane) initial state. Mitch Bradley
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* did some testing and discovered that holding for 16 SMB_CLK cycles
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* worked a lot more reliably, so that's what we do here.
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*/
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set_i2c_line(1, 1);
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for (x = 0; x < 16; x++) {
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udelay(5);
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set_i2c_line(1, 0);
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udelay(5);
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set_i2c_line(1, 1);
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}
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udelay(5);
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/* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
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outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
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}
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static void dcon_set_dconload_xo_1_5(int val)
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{
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gpio_set_value(VX855_GPIO(1), val);
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}
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static u8 dcon_read_status_xo_1_5(void)
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{
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u8 status;
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if (!dcon_was_irq())
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return -1;
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// i believe this is the same as "inb(0x44b) & 3"
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status = gpio_get_value(VX855_GPI(10));
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status |= gpio_get_value(VX855_GPI(11)) << 1;
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dcon_clear_irq();
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return status;
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}
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struct dcon_platform_data dcon_pdata_xo_1_5 = {
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.init = dcon_init_xo_1_5,
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.bus_stabilize_wiggle = dcon_wiggle_xo_1_5,
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.set_dconload = dcon_set_dconload_xo_1_5,
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.read_status = dcon_read_status_xo_1_5,
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};
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