404 lines
10 KiB
C
404 lines
10 KiB
C
/*
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* Copyright (C) 2004 by Basler Vision Technologies AG
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* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/ioport.h>
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#include <linux/err.h>
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#include <linux/jiffies.h>
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#include <linux/sched.h>
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#include <asm/types.h>
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#include <asm/rm9k-ocd.h>
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#include <excite.h>
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#include <rm9k_eth.h>
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#include <rm9k_wdt.h>
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#include <rm9k_xicap.h>
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#include <excite_nandflash.h>
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#include "excite_iodev.h"
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#define RM9K_GE_UNIT 0
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#define XICAP_UNIT 0
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#define NAND_UNIT 0
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#define DLL_TIMEOUT 3 /* seconds */
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#define RINIT(__start__, __end__, __name__, __parent__) { \
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.name = __name__ "_0", \
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.start = (__start__), \
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.end = (__end__), \
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.flags = 0, \
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.parent = (__parent__) \
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}
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#define RINIT_IRQ(__irq__, __name__) { \
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.name = __name__ "_0", \
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.start = (__irq__), \
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.end = (__irq__), \
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.flags = IORESOURCE_IRQ, \
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.parent = NULL \
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}
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enum {
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slice_xicap,
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slice_eth
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};
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static struct resource
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excite_ctr_resource = {
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.name = "GPI counters",
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.start = 0,
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.end = 5,
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.flags = 0,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_gpislice_resource = {
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.name = "GPI slices",
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.start = 0,
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.end = 1,
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.flags = 0,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_mdio_channel_resource = {
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.name = "MDIO channels",
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.start = 0,
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.end = 1,
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.flags = 0,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_fifomem_resource = {
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.name = "FIFO memory",
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.start = 0,
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.end = 767,
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.flags = 0,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_scram_resource = {
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.name = "Scratch RAM",
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.start = EXCITE_PHYS_SCRAM,
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.end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
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.flags = IORESOURCE_MEM,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_fpga_resource = {
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.name = "System FPGA",
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.start = EXCITE_PHYS_FPGA,
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.end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
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.flags = IORESOURCE_MEM,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_nand_resource = {
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.name = "NAND flash control",
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.start = EXCITE_PHYS_NAND,
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.end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
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.flags = IORESOURCE_MEM,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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},
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excite_titan_resource = {
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.name = "TITAN registers",
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.start = EXCITE_PHYS_TITAN,
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.end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
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.flags = IORESOURCE_MEM,
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.parent = NULL,
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.sibling = NULL,
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.child = NULL
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};
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static void adjust_resources(struct resource *res, unsigned int n)
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{
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struct resource *p;
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const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
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| IORESOURCE_IRQ | IORESOURCE_DMA;
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for (p = res; p < res + n; p++) {
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const struct resource * const parent = p->parent;
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if (parent) {
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p->start += parent->start;
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p->end += parent->start;
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p->flags = parent->flags & mask;
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}
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}
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}
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#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
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static struct resource xicap_rsrc[] = {
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RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
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RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
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RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
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RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
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RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
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RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
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RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
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RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
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RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ)
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};
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static struct platform_device xicap_pdev = {
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.name = XICAP_NAME,
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.id = XICAP_UNIT,
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.num_resources = ARRAY_SIZE(xicap_rsrc),
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.resource = xicap_rsrc
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};
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/*
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* Create a platform device for the GPI port that receives the
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* image data from the embedded camera.
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*/
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static int __init xicap_devinit(void)
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{
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unsigned long tend;
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u32 reg;
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int retval;
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adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
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/* Power up the slice and configure it. */
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reg = titan_readl(CPTC1R);
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reg &= ~(0x11100 << slice_xicap);
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titan_writel(reg, CPTC1R);
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/* Enable slice & DLL. */
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reg= titan_readl(CPRR);
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reg &= ~(0x00030003 << (slice_xicap * 2));
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titan_writel(reg, CPRR);
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/* Wait for DLLs to lock */
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tend = jiffies + DLL_TIMEOUT * HZ;
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while (time_before(jiffies, tend)) {
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if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
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break;
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yield();
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}
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if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
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printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
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xicap_pdev.name, DLL_TIMEOUT);
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retval = -ETIME;
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} else {
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/* Register platform device */
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retval = platform_device_register(&xicap_pdev);
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}
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return retval;
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}
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device_initcall(xicap_devinit);
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#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
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#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
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static struct resource wdt_rsrc[] = {
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RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
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RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
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RINIT_IRQ(TITAN_IRQ, WDT_RESOURCE_IRQ)
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};
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static struct platform_device wdt_pdev = {
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.name = WDT_NAME,
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.id = -1,
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.num_resources = ARRAY_SIZE(wdt_rsrc),
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.resource = wdt_rsrc
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};
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/*
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* Create a platform device for the GPI port that receives the
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* image data from the embedded camera.
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*/
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static int __init wdt_devinit(void)
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{
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adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
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return platform_device_register(&wdt_pdev);
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}
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device_initcall(wdt_devinit);
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#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
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static struct resource excite_nandflash_rsrc[] = {
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RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS, &excite_nand_resource)
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};
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static struct platform_device excite_nandflash_pdev = {
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.name = "excite_nand",
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.id = NAND_UNIT,
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.num_resources = ARRAY_SIZE(excite_nandflash_rsrc),
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.resource = excite_nandflash_rsrc
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};
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/*
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* Create a platform device for the access to the nand-flash
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* port
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*/
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static int __init excite_nandflash_devinit(void)
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{
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adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
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/* nothing to be done here */
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/* Register platform device */
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return platform_device_register(&excite_nandflash_pdev);
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}
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device_initcall(excite_nandflash_devinit);
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static struct resource iodev_rsrc[] = {
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RINIT_IRQ(FPGA1_IRQ, IODEV_RESOURCE_IRQ)
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};
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static struct platform_device io_pdev = {
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.name = IODEV_NAME,
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.id = -1,
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.num_resources = ARRAY_SIZE(iodev_rsrc),
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.resource = iodev_rsrc
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};
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/*
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* Create a platform device for the external I/O ports.
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*/
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static int __init io_devinit(void)
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{
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adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
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return platform_device_register(&io_pdev);
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}
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device_initcall(io_devinit);
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#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
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static struct resource rm9k_ge_rsrc[] = {
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RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
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RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
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RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
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RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
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RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
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RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
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RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
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RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
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RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
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RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
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RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
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RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
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RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
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RINIT_IRQ(TITAN_IRQ, RM9K_GE_RESOURCE_IRQ_MAIN),
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RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
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};
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static struct platform_device rm9k_ge_pdev = {
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.name = RM9K_GE_NAME,
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.id = RM9K_GE_UNIT,
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.num_resources = ARRAY_SIZE(rm9k_ge_rsrc),
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.resource = rm9k_ge_rsrc
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};
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/*
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* Create a platform device for the Ethernet port.
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*/
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static int __init rm9k_ge_devinit(void)
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{
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u32 reg;
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adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
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/* Power up the slice and configure it. */
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reg = titan_readl(CPTC1R);
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reg &= ~(0x11000 << slice_eth);
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reg |= 0x100 << slice_eth;
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titan_writel(reg, CPTC1R);
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/* Take the MAC out of reset, reset the DLLs. */
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reg = titan_readl(CPRR);
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reg &= ~(0x00030000 << (slice_eth * 2));
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reg |= 0x3 << (slice_eth * 2);
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titan_writel(reg, CPRR);
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return platform_device_register(&rm9k_ge_pdev);
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}
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device_initcall(rm9k_ge_devinit);
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#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
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static int __init excite_setup_devs(void)
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{
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int res;
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u32 reg;
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/* Enable xdma and fifo interrupts */
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reg = titan_readl(0x0050);
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titan_writel(reg | 0x18000000, 0x0050);
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res = request_resource(&iomem_resource, &excite_titan_resource);
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if (res)
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return res;
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res = request_resource(&iomem_resource, &excite_scram_resource);
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if (res)
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return res;
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res = request_resource(&iomem_resource, &excite_fpga_resource);
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if (res)
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return res;
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res = request_resource(&iomem_resource, &excite_nand_resource);
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if (res)
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return res;
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excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
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( IORESOURCE_IO | IORESOURCE_MEM
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| IORESOURCE_IRQ | IORESOURCE_DMA);
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excite_nand_resource.flags = excite_nand_resource.parent->flags &
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( IORESOURCE_IO | IORESOURCE_MEM
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| IORESOURCE_IRQ | IORESOURCE_DMA);
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return 0;
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}
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arch_initcall(excite_setup_devs);
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