bca10b906f
Handling System MMUs with an identifier is not flexible to manage System MMU platform devices because of the following reasons: 1. A device driver which needs to handle System MMU must know the ID. 2. A System MMU may not present in some implementations of Exynos family. 3. Handling System MMU with IOMMU API does not require an ID. This patch is the result of removing ID of System MMUs. Instead, a device driver that needs to handle its System MMU must use IOMMU API while its descriptor of platform device is given. This patch also includes the following enhancements: - A System MMU device becomes a child if its power domain device. - clkdev Signed-off-by: KyongHo Cho <pullip.cho@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
219 lines
5.7 KiB
C
219 lines
5.7 KiB
C
/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/mmc/host.h>
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#include <linux/platform_device.h>
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#include <linux/serial_core.h>
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#include <linux/smsc911x.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/gpio-cfg.h>
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#include <plat/regs-serial.h>
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#include <plat/regs-srom.h>
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#include <plat/sdhci.h>
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#include <mach/map.h>
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#include "common.h"
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/* Following are default values for UCON, ULCON and UFCON UART registers */
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#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
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S3C2410_UCON_RXILEVEL | \
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S3C2410_UCON_TXIRQMODE | \
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S3C2410_UCON_RXIRQMODE | \
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S3C2410_UCON_RXFIFO_TOI | \
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S3C2443_UCON_RXERR_IRQEN)
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#define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8
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#define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
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S5PV210_UFCON_TXTRIG4 | \
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S5PV210_UFCON_RXTRIG4)
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static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = ARMLEX4210_UCON_DEFAULT,
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.ulcon = ARMLEX4210_ULCON_DEFAULT,
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.ufcon = ARMLEX4210_UFCON_DEFAULT,
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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.ucon = ARMLEX4210_UCON_DEFAULT,
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.ulcon = ARMLEX4210_ULCON_DEFAULT,
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.ufcon = ARMLEX4210_UFCON_DEFAULT,
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},
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[2] = {
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.hwport = 2,
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.flags = 0,
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.ucon = ARMLEX4210_UCON_DEFAULT,
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.ulcon = ARMLEX4210_ULCON_DEFAULT,
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.ufcon = ARMLEX4210_UFCON_DEFAULT,
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},
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[3] = {
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.hwport = 3,
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.flags = 0,
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.ucon = ARMLEX4210_UCON_DEFAULT,
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.ulcon = ARMLEX4210_ULCON_DEFAULT,
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.ufcon = ARMLEX4210_UFCON_DEFAULT,
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},
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};
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static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
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.cd_type = S3C_SDHCI_CD_PERMANENT,
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.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
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#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
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.max_width = 8,
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.host_caps = MMC_CAP_8_BIT_DATA,
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#endif
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};
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static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
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.cd_type = S3C_SDHCI_CD_GPIO,
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.ext_cd_gpio = EXYNOS4_GPX2(5),
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.ext_cd_gpio_invert = 1,
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.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
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.max_width = 4,
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};
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static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
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.cd_type = S3C_SDHCI_CD_PERMANENT,
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.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
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.max_width = 4,
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};
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static void __init armlex4210_sdhci_init(void)
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{
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s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
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s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
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s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
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}
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static void __init armlex4210_wlan_init(void)
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{
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/* enable */
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s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
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s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
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/* reset */
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s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
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s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
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/* wakeup */
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s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
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s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
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}
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static struct resource armlex4210_smsc911x_resources[] = {
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[0] = {
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.start = EXYNOS4_PA_SROM_BANK(3),
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.end = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_EINT(27),
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.end = IRQ_EINT(27),
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.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
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},
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};
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static struct smsc911x_platform_config smsc9215_config = {
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
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.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
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.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
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.phy_interface = PHY_INTERFACE_MODE_MII,
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.mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
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};
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static struct platform_device armlex4210_smsc911x = {
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.name = "smsc911x",
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.id = -1,
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.num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources),
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.resource = armlex4210_smsc911x_resources,
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.dev = {
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.platform_data = &smsc9215_config,
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},
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};
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static struct platform_device *armlex4210_devices[] __initdata = {
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&s3c_device_hsmmc0,
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&s3c_device_hsmmc2,
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&s3c_device_hsmmc3,
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&s3c_device_rtc,
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&s3c_device_wdt,
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&samsung_asoc_dma,
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&armlex4210_smsc911x,
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&exynos4_device_ahci,
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};
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static void __init armlex4210_smsc911x_init(void)
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{
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u32 cs1;
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/* configure nCS1 width to 16 bits */
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cs1 = __raw_readl(S5P_SROM_BW) &
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~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
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cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
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(0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
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(1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
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(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
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S5P_SROM_BW__NCS1__SHIFT;
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__raw_writel(cs1, S5P_SROM_BW);
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/* set timing for nCS1 suitable for ethernet chip */
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__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
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(0x9 << S5P_SROM_BCX__TACP__SHIFT) |
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(0xc << S5P_SROM_BCX__TCAH__SHIFT) |
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(0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
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(0x6 << S5P_SROM_BCX__TACC__SHIFT) |
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(0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
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(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
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}
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static void __init armlex4210_map_io(void)
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{
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exynos_init_io(NULL, 0);
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s3c24xx_init_clocks(24000000);
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s3c24xx_init_uarts(armlex4210_uartcfgs,
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ARRAY_SIZE(armlex4210_uartcfgs));
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}
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static void __init armlex4210_machine_init(void)
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{
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armlex4210_smsc911x_init();
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armlex4210_sdhci_init();
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armlex4210_wlan_init();
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platform_add_devices(armlex4210_devices,
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ARRAY_SIZE(armlex4210_devices));
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}
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MACHINE_START(ARMLEX4210, "ARMLEX4210")
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/* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
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.atag_offset = 0x100,
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.init_irq = exynos4_init_irq,
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.map_io = armlex4210_map_io,
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.handle_irq = gic_handle_irq,
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.init_machine = armlex4210_machine_init,
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.timer = &exynos4_timer,
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.restart = exynos4_restart,
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MACHINE_END
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